CAPEC-671: Requirements for ASIC Functionality Maliciously Altered |
 Description An adversary with access to functional requirements for an application specific integrated circuit (ASIC), a chip designed/customized for a singular particular use, maliciously alters requirements derived from originating capability needs. In the chip manufacturing process, requirements drive the chip design which, when the chip is fully manufactured, could result in an ASIC which may not meet the user’s needs, contain malicious functionality, or exhibit other anomalous behaviors thereby affecting the intended use of the ASIC. Likelihood Of Attack Typical Severity Prerequisites
| An adversary would need to have access to a foundry’s or chip maker’s requirements management system that stores customer requirements for ASICs, requirements upon which the design of the ASIC is based. |
Skills Required
[Level: High] An adversary would need experience in designing chips based on functional requirements in order to manipulate requirements in such a way that deviations would not be detected in subsequent stages of ASIC manufacture and where intended malicious functionality would be available to the adversary once integrated into a system and fielded. |
Consequences  This table specifies different individual consequences associated with the attack pattern. The Scope identifies the security property that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in their attack. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a pattern will be used to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.| Scope | Impact | Likelihood |
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Integrity | Alter Execution Logic | |
Mitigations
| Utilize DMEA’s (Defense Microelectronics Activity) Trusted Foundry Program members for acquisition of microelectronic components. |
| Ensure that each supplier performing hardware development implements comprehensive, security-focused configuration management including for hardware requirements and design. |
| Require that provenance of COTS microelectronic components be known whenever procured. |
| Conduct detailed vendor assessment before acquiring COTS hardware. |
Example Instances
| An adversary with access to ASIC functionality requirements for various customers, targets a particular customer’s ordered lot of ASICs by altering its functional requirements such that the ASIC design will result in a manufactured chip that does not meet the customer’s capability needs. |
Taxonomy Mappings CAPEC mappings to ATT&CK techniques leverage an inheritance model to streamline and minimize direct CAPEC/ATT&CK mappings. Inheritance of a mapping is indicated by text stating that the parent CAPEC has relevant ATT&CK mappings. Note that the ATT&CK Enterprise Framework does not use an inheritance model as part of the mapping to CAPEC.Relevant to the ATT&CK taxonomy mapping | Entry ID | Entry Name |
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| 1195.003 | Supply Chain Compromise: Compromise Hardware Supply Chain |
References  Content History | Submissions |
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| Submission Date | Submitter | Organization |
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| 2021-06-24 (Version 3.5) | CAPEC Content Team | The MITRE Corporation | | | Modifications |
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| Modification Date | Modifier | Organization |
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| 2022-02-22 (Version 3.7) | CAPEC Content Team | The MITRE Corporation | | Updated References | | 2022-09-29 (Version 3.8) | CAPEC Content Team | The MITRE Corporation | | Updated Taxonomy_Mappings |
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