What is UCIe (Universal Chiplet Interconnect Express)? An open specification for die-to-die interconnect enabling high bandwidth density, low-latency, low-power communication between chiplets within a package.
UCIe (Universal Chiplet Interconnect Express) is an open specification for a die-to-die interconnect between chiplets within a package. It was developed to establish a ubiquitous interconnect at the package level and covers the die-to-die I/O physical layer, die-to-die protocols, and software stack needed to carry a variety of data including PCIe, CXL, Ethernet, and even proprietary protocols. UCIe specifies I/O interconnects with low latency, low power, high bandwidth density, and a variety of reaches within a package. Introduced in 2022, this open industry interface standard establishes a universal interconnect at the package level to support an interoperable, multi-vendor chiplet ecosystem.
Chip designers add UCIe capabilities to their silicon designs (GPUs, accelerators, ASICs, SoCs, FPGAs, etc.) by incorporating UCIe PHY IP, built to the published specification either in-house or sourced from IP vendors such as Cadence, Synopsys, Alphawave Semi, and Blue Cheetah. UCIe allows chip-to-chip communication between two UCIe-compliant chiplets, such as Ayar Labs’ TeraPHY™ optical I/O chiplets, with a UCIe-compliant GPU or other accelerator.
UCIe is a chip-to-chip interface built from the ground up and is compatible with optical links. It also has a clear scaling roadmap to address the need for increasingly higher bandwidth and shoreline density. Ayar Labs’ roadmap includes multiple generations of UCIe-compliant TeraPHY optical I/O chiplets with increasingly higher bandwidth and shoreline density.
UCIe-compliant TeraPHY optical I/O chiplets enable new architectures such as scale-up fabrics needing tens of terabits per second of connectivity in AI compute clusters and memory disaggregation, all while improving utilization and reducing power consumption and latency. Designers can use TeraPHY optical I/O chiplets for these architectures thanks to the UCIe standard.
Related:
Ayar Labs Unveils World’s First UCIe Optical Chiplet for AI Scale-Up Architectures | Press Release
UCIe 3.0 Specification | Specification
UCIe 3.0 Specification: Driving Innovation for Efficient, Scalable, and Reliable Chiplet Integration | White Paper
UCIe Consortium Releases 3.0 Specification With 64 GT/s Performance and Enhanced Manageability | Press Release
UCIe 3.0 Statements of Support | Press Release
AI Scale-Up and Memory Disaggregation: Two Use Cases Enabled by UCIe and Optical I/O | Blog
The Future of Chip Connectivity: UCIe and Optical I/O FAQs Explained | Blog
Enabling Optical Interconnects Using the New UCIe Standard | Blog
Meet UCIe Consortium Member Ayar Labs | UCIe Consortium Blog
UCIe Consortium | Website