Introduction#
PeakRDL-regblock-vhdl is a free and open-source control & status register (CSR) compiler. This code generator translates your SystemRDL register description into a synthesizable VHDL RTL module that can be easily instantiated into your hardware design.
Generates fully synthesizable VHDL RTL (IEEE 1076-2008)
Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
Configurable pipelining options for designs with fast clock rates.
Broad support for SystemRDL 2.0 features
Quick Start#
The easiest way to use PeakRDL-regblock-vhdl is via the PeakRDL command line tool:
# Install PeakRDL-regblock-vhdl along with the command-line tool
python3 -m pip install peakrdl-regblock-vhdl[cli]
# Export!
peakrdl regblock-vhdl atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
Depending on the chosen CPU interface, the generated RTL may rely on VHDL packages available in the hdl-src folder in the repository.
Looking for SystemVerilog?#
This project generates VHDL RTL. If you prefer using SystemVerilog, check out the upstream project from which this exporter was forked: PeakRDL-regblock