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20 Most Popular Articles
Updated: Mon, 09 May 2011 01:00:01 +0200
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| 1 | 1 |
How to calculate CPU utilization How to calculate CPU utilization |
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| 2 | 2 |
Understanding cascaded integrator-comb filters Understanding cascaded integrator-comb filters |
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3 | 9 |
FPGA programming step by step FPGA programming step by step |
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4 | 13 |
FPGA's vs. ASIC's FPGA's vs. ASIC's |
| 5 | 5 |
Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 This paper will review the new DDR3 features and compare and contrast them to previous features available in the DDR2 specification. One of the biggest changes is the in Physical Layer (PHY) portion of the memory interface and these changes will be high-lighted and illustrated with an example design of a high performance processor interface. The areas where backwards compatibility should be maintained will also be illustrated with an example design, showing how simple changes can provide significant benefits in re-use and system flexibility. |
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6 | 4 |
FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand |
| 7 | 7 |
Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment The ability to design high quality IP and to enable work practices for reuse methodology helps to achieve working SoCs in a timely and efficient manner. This paper describes a methodology for implementing IP reuse practices suited to an academic environmen |
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8 | 11 |
TLM 2.0 Standard into Action: Designing Efficient Processor Simulators This article presents TRAP (Transactional Automatic Processor generator), an innovative ADL targeted to the creation of fast and flexible simulators based on the SystemC language and on the new OSCI Transaction Level Modeling methodology. The modeling of the LEON2 and LEON3 processors is presented to show and assess the features, performance, and capabilities of TRAP. |
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9 | 6 |
Techniques to make clock switching glitch free Techniques to make clock switching glitch free |
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10 | 3 |
Architecture and Implementation of the ARM Cortex-A8 Microprocessor The Cortex-A8 processor spans a range of performance points depending on the implementation, delivering over to 2000 Dhrystone MIPS (DMIPS) of performance for demanding consumer applications and consuming less than 300mW for low-power mobile devices |
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11 | New!!! |
VLSI implementation of OFDM modem by Aseem Pandey, Shyam Ratan Agrawalla & Shrikant Manivannan from Wipro Technologies |
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12 | New!!! |
FPGA Clock Schemes FPGA Clock Schemes |
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13 | 14 |
SATA Connectivity solutions for Xilinx FPGAs This Whitepaper gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for building a complete, reliable, high-performance SATA solution by utilizing a design platform from Missing Link Electronics (MLE). |
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14 | 8 |
A comparison of Network-on-Chip and Busses This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris� NoC, the first commercial implementation of such architectures |
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15 | 16 |
Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc. |
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16 | 17 |
DDR2 Signal Integrity This paper highlights a typical design approach that can be adopted for an embedded PC (X86 based) board memory subsystem using a VIA VX700 system controller DDR2 interface. Boards with this chipset can feature either an Intel Pentium processor or VIA processor on front side bus (FSB). |
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17 | New!!! |
Hardware Co-Verification using VMM HAL-SCEMI On ChipIT Platform This article talks about VIP architecture requirement for achieving Hardware Accelarated Verification using on board generation, error checker, data checker and coverage collection, taking example of AHB Synthe-sizable VIP |
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18 | New!!! |
Encrypting data with the Blowfish algorithm Encrypting data with the Blowfish algorithm |
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19 | New!!! |
ARM Cortex-R4, A mid-range processor for deeply-embedded applications The ARM� Cortex�-R4 processor enables a wide range of deeply-embedded applications to be implemented with reduced system and development cost. Product applicability includes hard-disk drives, networking products, wireless and automotive applications. |
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20 | New!!! |
Systolic FIR Filter Based FPGA In this paper, we review in detail the basic building blocks of reconfigurable devices, essentially, the field-programmable gate arrays, then we describes a high-speed, reconfigurable Systolic Finite Impulse Response Filter design implemented in the Virtex-II series of FPGAs. |
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