Navraj Nandra, Director of Marketing for Mixed-Signal and Analog IP at Synopsys will discuss the latest trends in the semiconductor industry and how they are influencing the use of third-party IP in complex SoCs. Companies are increasingly outsourcing IP in order to focus engineering efforts on their core competencies and product differentiation. Mr. Nandra will discuss how Synopsys is delivering high-quality interface and analog IP solutions that enable designers to integrate the latest functionality into their SoC while reducing risk and improving time-to-market.
MoSys� presentation, �SerDes in High Reliability, Long Reach Applications,� explores the challenges facing designers implementing systems that are compliant to 10GBASE-KR and CEI11-LR standards. System timing and noise issues will be explained in detail, along with the architectural and circuit techniques required to meet the stringent requirements associated with PLL implementation and receiver equalization.
Post-silicon debug and verification is often kept hush-hush , despite the huge impact and urgency of this aspect of SoC development. As EE Times mentioned as early as 2007 ?post-silicon debugging is a dirty little secret that can cost $15 to $20 million and take six months to complete.? Time spent on post-silicon verification represents hidden waste, and may consume 35% of total project time.
Only the largest, best managed (and perhaps bravest) companies plan proactively for post-silicon debug. The key is identifying new solutions to support collaboration between the lab and designers. These solutions must be effective for both large companies with dedicated silicon verification groups; and companies where tapeouts are fewer and the project team alone hits the hot seat at silicon bring-up.
This session reviews the current methodologies for silicon debug and verification with a detailed look at formal verification technology, one new approach for solving these too-often unspoken and urgent scenarios.
* R. Goering, ?Post-Silicon Debugging Worth a Second Look?, EETimes, Feb. 05, 2007.
Mobile devices (iPhone, Android) are offering enriched connectivity and media experiences. All of this is placing tremendous demand on communications infrastructure (4G LTE) as well as enhanced localized processing, which in turn is fueling the demand for system level solutions. To meet these changes, the IP industry is increasing focused on higher performance analog solutions, and in turn seeing more mergers and consolidations then ever in the past� It is no longer about IP companies providing technology to Semiconductor companies, it is now about IP companies providing solutions and being acquired by System companies.
Today�s fully-functional embedded SoCs, such as those found in next-generation video devices, require enormous amounts of memory. Limited available bandwidth at the DRAM memory continues to be one of the most significant challenges plaguing SoC designers. Today�s SoCs have 50, 100 or even more cores, each demanding carefully tuned access to higher bandwidth DRAMs. Burst sizes in DDR3 systems have doubled, introducing an efficiency penalty that can dramatically compromise system performance. Increasingly, SoC designers are looking for innovative memory technologies to better maintain and even optimize on-chip performance while also increasing memory bandwidth� without additional costs or system degradation. The presenter will detail the latest memory innovations to eliminate DRAM performance bottlenecks in SoCs, and introduce a cost-sensitive solution for increasing memory bandwidth on-chip in the world�s most popular home entertainment and portable devices.
The complexity of Systems-on-Chip (SoC), their PCB interconnections and their integration as part of Chipsets require expertise beyond the mastery of silicon, especially in connection with Power, Reference and Clock networks in high-resolution audio systems. Typically designers of consumer systems - now mostly around audio subsystems - must face the sensitivities in connecting peripheral devices. Because of the intimate link between the electronic parts and the mechanical parts for sound conversion, some behavioral modeling of these parts is necessary to simulate the application schematics with a mix of electronic and mechanical models. By mastering the modeling and simulation of critical interfaces and devices, ViC performances can be maintained up to chipset level, and the cost of each project can be sharply decreased, as sources of disturbances are eliminated by simulation without postponing to the prototyping stage. This session reviews the Power, Reference and Clock networks as well as the challenge of modeling and simulating multi-domain application schematics.
Portable, handheld or battery powered systems today routinely include wireless connectivity such as Bluetooth. Wireless protocols like Bluetooth define low power modes such as Sniff, Hold or Park and wireless interface controller SOCs attempt to provide sleep mode states for these low power modes of the protocol. These sleep mode states utilize standard power save techniques such as clock and power gating, with varying degrees of actual power save depending on the wake up time constraints and duty cycle requirements of the application. The efficacy of these techniques are rather limited to simple use cases scenarios and does not address potential for power save while in active modes. Worse still, a poorly designed or an ill behaved remote device can influence the power drain of this device, because of higher level of activity. Therefore, power saving while in active modes becomes critical.
We put forth several principles for designing wireless interfaces for lowering power while in active modes. We further observe that while IP cores may be optimized for power save, the interfaces between the IP cores and the rest of the SOC may not be adequately optimized. We also highlight module interface design principles towards power aware interface design.
We explain these principles using the case of Bluetooth System on Chip design.
Customers now expect a user experience whether in the home or on the move just like they have on their PC's and laptops - but easier to use. This is driving the need for dedicated graphics and video hardware in next generation SoC designs to support an intuitive, more graphically enhanced user interface and personal entertainment experience. Furthermore, consumers expect to download applications and access "cloud" based services with ease and more quickly than on the PC. In short ARM's semiconductor customers are being asked to create high performance and lower power general purpose computing platforms. For the record, fans, booster/big battery packs and ozone depleting power consumption is not allowed! You, the product designer, must now respond by squeezing out every last drop of performance from your system design. This requires that you have a much greater understanding of the way that the software and hardware system behave under a wider range of consumer use cases AND also requires a level of control to partition the system resources, such as memory, in as optimal a way as possible as the system is stretched to its limits! Please remember we need to be good to the environment, avoid fans, deliver value for money and above all a user experience better than on the PC! Buckle up we are going on a ride.
Microprocessor vendors are proposing low-power multicores, FPGA are now able to handle consumer and low-power designs while SoCs continue to offer the lowest cost, lowest power and highest performance but are hampered by design costs. The key question is how to find the best hardware to implement a given function and how to get that function on the hardware. Each of these solutions is coming from a totally different point of view but are equally pressured by cost, performance and power tradeoffs. The panel will address the applicability of these solutions and the evolution of the design methodology to a programming paradigm
Embedded software quality and platform optimisation are key to consumer products� success and differentiation. To deliver such optimised products embedded software and hardware engineers require real-time visibility on how the embedded software and hardware interact, both during the product development cycle and in the final products for new applications, maintenance or failure analysis.
In price sensitive, consumer markets this must be achieved with minimal increase in engineering or unit manufacturing costs.
In this panel, industry leaders in embedded software and hardware development (OEMs, silicon suppliers, IP providers and tool vendors) will analyse market requirements and will debate on how cost effective on-chip visibility can be provided to all the SoC developers and users.
Recent surveys* confirm that an increasing portion of the chip development effort is spent on embedded software development. As a result, prototyping techniques have emerged at several levels of abstraction, enabling embedded software development to commence far ahead of prototype silicon and to increase productivity of hardware/software debug. With re-use for hardware development approaching the 50% mark, availability of processor, on-chip bus, digital and mixed-signal connectivity IP at several levels of abstractions shortens the time to availability of system prototyping platforms. Virtual platforms are enabled by IP at the transaction-level, while FPGA prototypes utilize IP at the register transfer level (RTL). Together they enable system prototypes for pre-silicon software development and verification. This keynote will review advanced technologies and trends of IP re-use and system prototyping for embedded software development and verification. It will chart a course of the key trends towards next generation digital and mixed signal IP development and verification.
* 2008 SNUGs, 2009 DVCon
The semiconductor IP industry has quietly and quickly grown to well over $1B in annual revenue with the Design & Reuse website listing over 6,500 IP components available from more than 400 suppliers. However, there is only a single vendor with double-digit market share which suggests a very young and dynamic long-tail of companies racing towards future leadership market positions. This presentation elaborates the fundamental economic forces behind the emergence of the semiconductor IP industry, very briefly touch upon how the ARM business model works, while examining at length exactly why it works. This is considered alongside practical insight into how other IP categories and business models can be immediately optimized to better deliver value to the customer. By understanding the economic forces in play and why the semiconductor IP business model works, the audience will be able to enhance their strategy for future growth and success.
With the downturn in the global economy, companies must seek ways to improve time-to-market by decreasing design time. By outsourcing critical IP, SoC designers can accomplish this goal. But there must be collaboration between the IP vendor and the customer, especially if IP reuse is to be achieved. Both must understand the needs of the other whether they're economic or technologic. This panel will take a fresh look at design and reuse from a business and technology perspective. Topics covered will include:
- Why outsource in the first place? What are the advantages?
- What degree of collaboration is needed between the IP vendor and customer?
- Do standards solve design compatibility issues, or do they create them?
- What are the design considerations for integrating IP cores when hundreds of cores are involved?
- Tools for design. What is the responsibility of the IP vendor to provide them? Are third party tools adequate?
- License fees or royalties; the pros and cons of each from the vendor and customer perspective
- Building a successful IP business; what does the future hold?
SoC's of today are really systems and hence require many more components besides RTL IPs. The panel will discuss synthesizable RTL, verification IPs, analog IPs, software stacks, hardware platforms and tools required for a successful SoC design. The panelists will provide a vendor's perspective as well as a designer's perspective on the importance of total IP solutions required to enable technology adoption.
While embedded systems has involved multiple operating systems for quite some time, the emergence of multicore system-on-chip (SoC) creates renewed interest along with challenges and opportunities for system architecture. This keynote presentation will discuss the various software architectures that can be implemented on multicore platforms: AMP with IPC, SMP and a mix of AMP and SMP. Challenges and opportunities for optimizing each type of architecture will also be explored. A key emphasis in this presentation will be on how to interface a real-time operating system (RTOS) with a Linux-based (open source) application framework like Android, and why it makes sense to have both environments tightly integrated.
The maturing semiconductor industry and weak financial markets with limited funding options raise questions regarding further viability of the fabless model. Is there still room for entrepreneurial juices to flow in the semiconductor business or are we more or less becoming like the automobile industry? The industry evolution took us from the IDM model to pure-play foundry, fabless, and IP provider (chipless) business models. Many of these models are currently experiencing serious issues and the pundits are pointing to alternative approaches seeking inspiration from publishing, pharmaceutical, or Hollywood movie production models. This panel will explore these issues from the perspective of both mature and early-stage semiconductor companies today.
Especially in this economy, IP deployment is critical for time to market and reduced development costs. However, there is a huge difference between reusing IP (as is), and leveraging IP (with modifications.) What are the issues for IP reuse and IP leverage? How can IP be more easily consumed? Explored? Comprehended? Modified successfully, and then verified? Is IP transfer a transfer of technology, design knowledge , or design flow? How can verification IP be improved? IP quality? What solutions are coming from the IP and EDA vendor ecosystem?
|
