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20 Most Popular Articles
Updated: Sun, 10 Jul 2011 01:00:01 +0200
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| 1 | 1 |
How to calculate CPU utilization How to calculate CPU utilization |
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FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand |
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Understanding cascaded integrator-comb filters Understanding cascaded integrator-comb filters |
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FPGA programming step by step FPGA programming step by step |
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5 | 9 |
Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster This paper focuses on the verification of the Power Manager in the context of the MIPS32� 1004K� Coherent Processing System (CPS), in which various software and hardware events can control switching of power states. Without exhaustive verification of the Power Manager, power management functionality of the design cannot be guaranteed. This paper discusses how we successfully used formal methods to verify the Power Manager. |
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6 | 5 |
Techniques to make clock switching glitch free Techniques to make clock switching glitch free |
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7 | 10 |
SATA Connectivity solutions for Xilinx FPGAs This Whitepaper gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for building a complete, reliable, high-performance SATA solution by utilizing a design platform from Missing Link Electronics (MLE). |
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8 | 6 |
Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 This paper will review the new DDR3 features and compare and contrast them to previous features available in the DDR2 specification. One of the biggest changes is the in Physical Layer (PHY) portion of the memory interface and these changes will be high-lighted and illustrated with an example design of a high performance processor interface. The areas where backwards compatibility should be maintained will also be illustrated with an example design, showing how simple changes can provide significant benefits in re-use and system flexibility. |
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9 | New!!! |
H.264 High Profile: Codec for Broadcast & Professional Video Application High definition video content is becoming rampant as more and more countries are now transitioning into digital life. The ways to deliverHigh definition content in a bandwidth limited channel have become challenge in itself. To cater to such highly demanding broadcast & professional video markets, we require a compression / decompression standard that allows no compromise on the quality of the video that has to be broadcasted over a bandwidth constrained networks. |
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10 | New!!! |
Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc. |
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11 | 19 |
Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment The ability to design high quality IP and to enable work practices for reuse methodology helps to achieve working SoCs in a timely and efficient manner. This paper describes a methodology for implementing IP reuse practices suited to an academic environmen |
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12 | New!!! |
MIPI� MPHY - An introduction Recognizing the need for high bandwidth pipes, the MIPI alliance has been defining standards for these serial interfaces. D-PHY, which was ratified 1.5 years ago but with a near final version for 3 years, supports 1Gbps per lane. The M-PHY specification, whose 1.0 version is about to be ratified, supports about 1.25Gbps/1.5Gbps and has options to support 2.5Gbps/3Gbps and 5Gbps/6Gbps per lane. |
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13 | 17 |
ARM Mali-T604 tips mobile graphics, computing, and IP trends The ARM Mali graphics core is a departure from years of evolution in the rendering hardware, but points to the future of IP. |
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14 | 11 |
FPGA Clock Schemes FPGA Clock Schemes |
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15 | New!!! |
ASIC to COT: knowing your outsourcing options ASIC to COT: knowing your outsourcing options |
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16 | New!!! |
Designing A Real-Time HDTV 1080p Baseline H.264/AVC Encoder Core This paper describes an efficient implementation of a baseline H.264/AVC encoder core capable of encoding a 1920x1080 video stream in real time at 30 frames per second (HDTV 1080p). |
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17 | New!!! |
FPGA design from scratch I have been designing ASICs for more than 15 years. A few years ago I started to realize that there is another player in town and that is the FPGA circuit. With increasing NRE costs and with the long turn-around times, ASIC designs have become high-risk projects. At the same time FPGAs are getting bigger and faster and many companies have therefore decided to only use FPGAs. |
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18 | New!!! |
Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning |
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19 | New!!! |
FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus DLX is an open source microprocessor, it�s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the DLX microprocessor implemented with Wishbone bus interface for a SoC (System-on-Chip) design. |
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20 | New!!! |
Module Threading Technique to Improve DRAM Power and Performance This paper provides details of all DRAM timing constraints which have heavy impact on memory system performance and introduces module threading technique to overcome these limitations. It also provides detailed theoretical analysis on how module threading can offer finer granularity, higher bandwidth and importantly lower power consumption. It also provides board level analysis where 25% power was saved and a higher performance achieved by adopting module threading technique. |
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