Semiconductor Engineering

New technical papers recently added to Semiconductor Engineering’s library https://lnkd.in/dnCU-G8g #semiconductor #AIhardware #DRAM #3DDRAM #signalintegrity #interconnects #EUVlithography #CIM #photomasks #lithography Princeton University Haiyue Ma Lauren Malek Joey Forzani David Wentzlaff imec KU Leuven, Samsung Electronics, Lam Research University at Buffalo, University of Stuttgart, IBM Research Yuting Hu, Chenhui Xu, Hua Xiang Gi-Joon Nam Fraunhofer IISB ASML Andreas Erdmann, Varun Jadhav, Gerardo Bottiglieri National University of Singapore Yue Jiet Chong, Wei Zhang Xuanyao Fong Cornell University, IBM Research, The Johns Hopkins University, Penn State University Yeryun Cheon Mehrdad Kiani KTH Royal Institute of Technology Xinxin Liu Zifan Che Zofia Maj Kristinn B. Gylfason

Chip Industry Week In Review https://lnkd.in/gHXgz7jg DAC’s big buzz; CHIPS Act $; China’s immersion DUV; UMC expands; SIA’s state of the industry; MediaTek $5B expansion; DRAM shortages; earnings; PCB design credential program; IBM’s quantum advantage; AI security alliance; foreign robotics ban and more... #semiconductor #semiconductormanufacturing #AgenticAI #DAC63 Cadence Synopsys Inc Siemens Digital Industries Software Intel Foundry ASE Global Lens Technology Inc. Intel Qnity United Microelectronics Corporation (UMC) MediaTek Linde Semiconductor Industry Association SEMI GlobalFoundries Multibeam Extropic Thintronics® OBSIDIA Semiconductors Silvaco Inc ChipAgents Eliyan Corporation Multiverse Advantest Amkor Technology, Inc. Arm ZEISS Semiconductor Manufacturing Technology Infineon Technologies DAC, The Chips to Systems Conference SEALSQ Lava Accellera Axiomise Kyle Squires

Change is coming, but how quickly depends on the availability of data and when chipmakers are confident enough to let AI take over. By Brian Bailey. https://lnkd.in/guBzK-b8 #EDA #chipdesign #AgenticAI #verification #semiconductor Abhi Kolpekwar Siemens Digital Industries Software Ramesh Narayanaswamy Synopsys Inc Alexander Petr Keysight Technologies Andy Nightingale Arteris Paul G. Cadence William Yang Wang ChipAgents Stefan Birman AMIQ Consulting

As packages get larger and thinner, warpage is becoming a process-control problem rather than a simple flatness spec. By Gregory Haley, Ph.D. https://lnkd.in/gA9bpzTY #semiconductor #warpage #advancedpackaging #hybridbonding #substrates #HBM #PanelLevelPackaging #PLP #metrology #chiplets Hamed Gholami Derami, Ph.D. Brewer Science Wiwy Wudjud ASE Global Michael Kelly Amkor Technology, Inc. Lang Lin Synopsys Inc Wooptix

Success at the edge takes advantage of common threads — lithography, imaging, chiplets, and AI. By Laura Peters. https://lnkd.in/gJyUqEZ4 #semiconductor #physicalAI #ITFWorld #healthtech #humanoids Germain Fenger Synopsys Inc Vidya Rajagopalan Rivian Brewer Science imec Tina Babu Shylaja Milind Pandit Josh Gibson Hypervision Surgical Gates Foundation Salil Raje AMD Dr. Ahmad Bahai Texas Instruments #chiplets Dieter Hoffend #automotive #EVs

Scaling NoCs across chiplets requires earlier validation of coherency, congestion, thermal effects, and fault behavior. By Liz Allan. https://lnkd.in/d77YMdWZ #semiconductor #verification #EDA #NoCs Razvan Arhip Keysight Technologies Kent Orthner Baya Systems #interconnects Mick Posner Cadence Ashish Darbari Axiomise Frank Schirrmeister Synopsys Inc Andy Nightingale Arteris Matt Commens Satish Radhakrishnan, Ph.D Vinci4D.ai

Verifying Networks On Chip https://lnkd.in/gAjYPP2X Challenges increase significantly with chiplets and coherency. More data, more processing elements, and more memories are making it much harder to maintain consistent throughput in a multi-die assembly. There is more concurrent traffic, more potential interactions, and more protocol layers. Ashish Darbari, CEO of Axiomise, talks about the of coherency on serialization bugs, how to ensure data is secure, and how to ferret out the root cause of problems like silent data corruption using formal technology. #NoC #verification #formalverification #coherency #chiplets #semiconductor #SilentDataCorruption

Latest news: Amkor’s $1.5B deal; Intel Foundry revenue up 31%; Siemens’ dual buys; SiC plant dies; AMD’s big week; TSMC price hike; Nokia’s fab buy; earnings; $300M for accelerating inference; Keysight’s multiphysics; copper interconnect alternative and more... https://lnkd.in/g2e_x_Sx #semiconductor Amkor Technology, Inc. Intel Foundry Siemens Digital Industries Software IBM AMD Nokia NXP Semiconductors Keysight Technologies Intel Quadric ASML Hitachi Quantinuum UCLA Sergio Carbajo Mobileye Gijs Burghoorn Alessandra Dolmeta Prashanthi Metku Haiyue Ma Chang Eun Song Yeryun Cheon Arteris ChipAgents California Memory Technologies Inc. (memtech.ai) Skyworks Solutions, Inc. Astera Labs Cornelis Networks Real Intent Mach42 Soitec Texas Instruments Fortinet Gwan In Kim Ruben Van Assche Etched Cerebras IBM

Special Report: Photonics is forcing EDA to verify not just chips, but the physics of light inside full electro-optical systems. By Ann Mutschler. https://lnkd.in/gKsm2tW4 #photonicdesign #siliconphotonics #EDA #chipdesign #PICs #EOE #CPO #ElectroOpticalElectrical #verification Vishal C. Ayar Labs Kent Orthner Baya Systems Niels Fache Keysight Technologies John Bowers ChipAgents Gilles Lamant Cadence John Ferguson Siemens Digital Industries Software Ashish Darbari Axiomise Raha Vafaei Synopsys Inc Priyank Shukla

Where AI will be successful, who will benefit, and how that will affect the design process. Part 2 of the ESD Alliance Executive Outlook panel discussion. By Ed Sperling. How AI will alter chip design, where it will be successful, how AI agents will be managed, and who will oversee them, with Cindy Cui, vice president of global customer success at ChipAgents; Walden C. ( Wally ) Rhines, CEO of Silvaco Inc; Shelly Henry, CEO of Moores Lab AI; Dave Kelf, CEO of Breker Verification Systems; Vince Wong, head of AI development at Verific Design Automation, Inc; and Ann Wu, CEO of Silimate (YC S23). https://lnkd.in/gaGwH2Cz #EDA #chipdesign #AgenticAI #semiconductor ESD Alliance, a SEMI Technology Coalition #verification #HLS #highlevelsynthesis