We're celebrating the 30th anniversary of Tom's Hardware. Since the beginning of Tom’s Hardware in 1996, we’ve been covering CPUs. Over the course of the past 30 years, we’ve maintained a comprehensive list of the best CPUs for gaming by reviewing each new release, and we’ve compiled thousands of data points spanning years to compile our CPU benchmark hierarchy. From the Pentium II and the introduction of Dual Data Rate memory to dual 3D V-Cache CPUs, Tom’s Hardware has been there for it all.

It’s time to look back, not just on Tom’s Hardware’s role in the world of CPUs over the past 30 years, but on the broader CPU market. Earth-shattering releases at a given time turned out to be footnotes in hindsight, and bubbling competition that seemed like no real threat turned into seismic shifts in the AMD vs. Intel battle. Hopefully, along the way, we’ll see some reflections of what’s going on in the world of CPUs today.

This is a celebration of 30 years of CPU coverage here at Tom’s Hardware, a history lesson about how the AMD and Intel of yesteryear arrived at the positions they’re in today, and a retrospective of the CPUs that stood the test of time against the refreshes that faded into obscurity just as soon as they were released. We hope you enjoy it.

Ruffling feathers from day one (1996 - 1998)

Ruffling feathers from day one (1996 - 1998)

Like much of the early internet, the true beginnings of Tom’s Hardware (or, rather, Tom’s Hardware Guide) is difficult to pin down, but the earliest archived article concerns the SoftMenu BIOS, which allowed you to change CPU settings through software rather than physical jumper cables; it should go without saying that this article was from July 1, 1996. There were articles before this one, with the original domain of sysdoc.pair.com going online in February 1996.

Tom’s Hardware gained a lot of traction a year later with a CPU review: a look at the Intel Pentium II ‘Klamath’ processor.

Tom’s Hardware’s founder, Thomas Pabst, had discussed CPUs previously, like in a dense CPU guide published the same year, but the Intel Pentium II review marked a turning point. It was published March 1, 1997, more than two months before Intel launched the Pentium II 80522 (or Klamath). It was not positive: “...since I wouldn't eat [Mad Cow Disease] infected beef, I wouldn't be interested in risking an infection of my computer with this CPU either,” wrote Pabst.

The CPU wasn’t officially available, but Pabst was able to test the chip with a pre-release unit shared by two German magazines: C'T Magazin fur Computertechnik and PC Professionell. Following the publication of all three reviews, Intel targeted the two German magazines, threatening to withhold advertising dollars and take legal action against them. Pabst publicized this fiasco and was contacted by The New York Times, which also covered the story. Intel backed down. Pabst later wrote that “...this 'David against Goliath'-incident made Tom's Hardware Guide very famous.”

In the following months, Pabst focused on CPUs quite a bit, breaking from the performance-tuning guides and general enthusiast information the website had previously published. The situation with Intel made Pabst a “secret star,” so much so that AMD not only offered Pabst a free review unit of the upcoming K6, but also apparently offered to cover legal fees should Intel pursue the situation further.

Although the unofficial review of the Pentium II predates it, the first review that looks most like the technical reviews that have been published on Tom’s Hardware for decades came in April 1997 with a review of the AMD K6, a CPU that established AMD as a true competitor to Intel, claiming Pentium II-like speeds for less money.

The performance wasn’t quite on the level of a Pentium II, most notably because the K6 originally arrived at 233 MHz, when 266 MHz was promised. But it was competitive, particularly when compared to the Pentium II 233, and much cheaper. Pabst concluded the review, “All in all I'm sure that this CPU will be very successful… Whoever is contemplating the purchase of an Intel Pentium or Pentium MMX CPU can forget about this now. The AMD K6 is faster and cheaper.”

Later that same month, Pabst published a proper review of the Pentium II, now using finalized silicon. In DOS games and the 32-bit Windows NT, Pentium IIs showed a commanding lead over the K6, though the battle on Windows 95 was closer. “The world is back to normal. Intel’s managers can sleep quietly again. The Pentium II shows that Intel is still the leader in the CPU market,” the review concluded.

A review of the Cyrix/IBM 6x86MX went live in 1997, as well, showing competitive performance with the K6, but much of the rest of the year was focused elsewhere after the Pentium II/K6 showdown. Looking back, it’s interesting to note the dynamic at play between AMD and Intel, with Pabst using a running gag of referring to Intel as the “Empire,” and competitors like AMD and Cynix as “Rebels.” Although Intel backed away from further action on Pentium II, it wouldn’t be the last time Pabst and Intel butted heads.

The Pentium III incident (1999 - 2001)

The Pentium III incident (1999 - 2001)

The competitive performance of K6 brought AMD into focus as the rival to Intel, which Pabst often described as “almost-monopolistic” at the time. However, AMD really put itself on the map with the release of K7, or as it’s better known, Athlon, in June 1999. In our review, we described it as “a milestone in the whole processor scene,” due in part to AMD’s unique three-way instruction decoder, which allows instructions of variable complexity through all three lanes. Intel’s P6 architecture in Pentium III also had a three-way instruction decoder, but they were segmented based on the complexity of the instruction.

We’re still firmly in the single-core era of CPUs here, so an architectural divergence like this, even before testing, represented a goldmine of speed gains. Rather than releasing several variants of silicon sliced up in different ways, as we see with modern CPUs, Intel and AMD refined their chips and released new versions with faster clock speeds. AMD released the Athlon 600 as the fastest chip in the range at 600 MHz first, but less than two months later, it introduced the Athlon 650, and two months after that, the Athlon 700.

Intel was caught off guard and quickly introduced the Pentium III 600 to counter AMD. The original Pentium III range, codenamed Katmai, was largely a refinement of Pentium II ‘Deschutes’ chips; both were built using a 250nm node, in fact. In our original Athlon review, we noted instability with the Pentium III 600, suggesting the architecture couldn’t handle such high clock speeds.

The original ‘Katmai’ range of Pentium IIIs was short-lived, and later in 1999, Intel introduced a new revision called Coppermine. Coppermine introduced an on-chip L2 cache for Intel, and it was built on a 180nm node, allowing Intel to go from 9.5 million transistors on Katmai to 28 million on Coppermine, as well as push clock speeds up to 733 MHz with the initial range, squeezing out a minor increase over the Athlon 700. Less than two months later, AMD introduced Orion, or Athlon Model 2, which also used a 180nm node and clocked up to 750 MHz. This back and forth of minor clock speed improvements is going to stick with us for at least another half of a decade, so strap in.

The goal, of course, was the first 1 GHz CPU, a milestone that AMD claimed for itself in March 2000 with the introduction of the Athlon 1000. Intel had shown a 1 GHz Pentium III, but AMD released a 1 GHz Athlon first. Intel followed shortly after with its first CPU to hit the gigahertz milestone. Intel didn’t want to place second again, so it went to work on the Pentium III 1.13 GHz, which it introduced in July.

Pentium II made Tom’s Hardware a name in the PC industry, but the Pentium III 1.13 GHz gave it a name among enthusiasts. Our review found that the processor wasn’t stable at 1.13 GHz, and less than a month after introducing the chip, Intel recalled it. The Pentium 1.13 GHz would eventually come back in 2001, but at the pace of CPU innovation at the time, even a six-month delay was detrimental.

In June 2000, AMD introduced a refinement of Athlon, codenamed Thunderbird, and days before Intel’s recall, introduced the Athlon 1100. AMD remained uncontested throughout the rest of the year, pushing Thunderbird up to 1.2 GHz. Intel was closing the curtain on Pentium III and trying to move attention away from Athlon toward its upcoming Pentium 4 range.

Going for gigahertz (2001 - 2004)

Going for gigahertz (2001 - 2004)

Intel was struggling to keep pace with Athlon, but work was going on behind the scenes on the new NetBurst microarchitecture, which was set to become the successor to P6. It was introduced to the world with the Willamette core inside the first Pentium 4. Like most major microarchitecture shifts we’ve seen from Intel and AMD, NetBurst wasn’t an immediate success. However, Pabst noted in our review: “I am certain that Intel will deliver very fast Pentium 4 processors very soon. Intel has finally won back the ability to make AMD's life a lot harder.”

Intel pushed P6 down to a 130nm node with the release of Tualatin Pentium III chips, but the focus was on Pentium 4 and optimizing NetBurst. In March, AMD introduced the Athlon 1333, but Team Red was losing steam. Intel had already released a Pentium 4 1.5 GHz, and it introduced the Pentium 4 1.7 GHz (along with a price cut to the range) in April 2001. With a new microarchitecture seemingly bursting with potential, it was only a matter of time before Intel made its way back to the top.

That came in August, when Intel planted its flag on the 2 GHz milestone with Pentium 4, and beat out AMD’s fastest Athlon chip. AMD didn’t like that. Later in the year, in October, AMD introduced its Athlon XP range, and with it came a sneaky switch in marketing strategy. Rather than include the clock speed as part of the processor name (i.e., Athlon 1333), AMD started using model names. No, the Athlon XP 1500+ wasn’t clocked at 1.5 GHz; it was clocked at 1.3 GHz. This nomenclature climbed all the way to the top, with the Athlon XP 2100+, which was not 2.1 GHz, but rather 1.7 GHz.

At the time, AMD described this shift as an alignment with what it was able to deliver with Athlon. During this era, we start to see more significant architecture divergences between Intel and AMD, so much so that like-for-like clocks could result in vastly different performance. That’s what we found in our Athlon XP review, in fact, with the Athlon XP 1800+ (clocked at 1,533 MHz) contesting the Pentium 4 2 GHz. Still, it’s not hard to see what AMD was trying to do. In January 2002, Intel introduced its Northwood core for Pentium 4, which could clock up to 2.2 GHz. AMD wasn’t able to break the 2 GHz barrier yet, but it used product names to suggest it had.

Names weren’t enough. By the middle of 2002, Northwood had picked up steam and could clock as high as 2.8 GHz; even the 2.4 GHz Pentium 4 was able to beat AMD’s fastest Athlon XP 2100+ across our benchmarks. AMD was working on the Thoroughbred revision of Athlon XP, including a node shrink down to 130nm to match Intel’s new Northwood core, which it trickled out through 2002. By the end of the year, AMD had shown the Athlon XP 2800+ as a rival to the Pentium 4 2.8 GHz.

Despite lagging in clocks, AMD had become quite popular during this time due to the competitive performance of Athlon XP and (most importantly) a lower price point than the expensive Pentium 4s. Still, there was a stalemate in technology between Intel and AMD, and Intel would break it in November 2002 with the Pentium 4 3.06 GHz.

It was the first consumer CPU to clock to 3 GHz out of the box, adding another notch to Intel’s belt, but it was also the first CPU to bring Intel’s long-standing simultaneous multithreading implementation, called Hyper-Threading, to market. With higher clocks and two threads to play with, the Pentium 4 3.06 GHz cemented Intel at the top of the performance charts, beating out AMD’s fastest Athlon XP and even a 3.6 GHz Pentium 4 (no Hyper-Threading) in some benchmarks. Tom’s Hardware actually benchmarked the Pentium 4 3.6 GHz nearly a year before it was available, and had data in time to compare to the Pentium 4 3.06 GHz with Hyper-Threading.

More cores, more fun (2004 - 2007)

More cores, more fun (2004 - 2007)

The clock speed battle from the late 90s and early 2000s was starting to fall apart. AMD had demonstrated that performance was more than peak clocks with Athlon XP, and Intel was pushing ahead with Hyper-Threading to get more work done simultaneously each clock cycle. The first half of 2003 was dull in the world of CPUs as Intel worked on its Prescott core and AMD mulled over “ClawHammer,” which would eventually become Athlon 64.

Athlon 64 would be the first to bring AMD’s x86-64 ISA extension (called AMD64) to the desktop market (it previously showed up in Opteron). It rolled out in September 2003, and just a week before release, Intel launched the Pentium 4 Extreme Edition, which was widely considered a panic switch in response to Athlon 64 while Prescott was still under wraps. Although Intel maintained the performance crown with P4 Extreme against the Athlon 64 FX-51, it did so at a much higher price.

Still, this late-stage battle as Intel and AMD moved toward a 90nm node was important. Intel started marketing expensive, high-performance processors directly to enthusiasts in a market that would eventually get the HEDT, or high-end desktop, name. Meanwhile, AMD designated some Athlon XP chips with the FX name, which signaled high-performance chips with unlocked multipliers.

Intel was first to get down to 90nm with its highly anticipated Prescott core, though it arrived with a whimper. It clocked slower, allowing the FX-51 to remain competitive and Northwood chips to remain at the top of the charts in our review. There, our reviewer Patrick Schmid wrote: “In our opinion, Intel today does not care about Prescott as a processor, but as a marketing instrument. It is fast enough, which is mainly what counts, and since the 90 nm production process yields cheap processors in vast quantities, the Santa Clara-based company gains new flexibility.”

AMD made it down to 90nm later in the year with the FX-55. The FX-55 allowed AMD to close the gap with higher-clocked Pentium 4s, as we found in our review. However, it was becoming clear that the chase for higher clocks wouldn’t be enough. In our review, Schmid wrote in 2004: “Today, the performance gap between the fastest and the slowest processors in our benchmark charts is rather small.”

Intel fired back at the beginning of 2005 with Prescott 2M, a minor revision to the Prescott core with 64-bit ISA extensions, and released the Pentium 4 Extreme Edition 3.73. The tide shift came in the summer of 2005 when AMD launched the Athlon 64 X2, built on a 90nm node, and featuring two cores on the same package.

Intel had released its double-core Pentium D just weeks earlier, which was also a dual-core chip, but the design forced Intel to compromise clock speeds — an important spec given how few applications could actually leverage a dual-core chip in consumer software. AMD ultimately won the battle with the Athlon 64 X2, largely due to the fact that it could keep pace with single-core Athlons in most benchmarks, as you can see in our early preview of the chip.

AMD released more Athlon 64 X2 chips throughout 2005, while Intel rolled out various chips under different Pentium brands, including the Smithfield core on Pentium D. Intel built out the range into 2006, using another node shrink down to 65nm with the Presler core, which was the final revision under the Pentium brand. In January 2006, Tom’s Hardware first reported that Intel planned to drop the Pentium brand, a name that it had kept for over a decade.

In its place? The new Core microarchitecture, finally moving on from NetBurst, which had been plagued with thermal issues as clocks climbed. Built out of Intel’s work in mobile chips, the Core 2 Duo was Intel’s first proper dual-core processor — the “double-core” Pentium D was just two Pentium dies fused together. It was a tide shift.

As we found in our Core 2 Duo review, the base E6600 and E6700 often beat, or at least matched, AMD’s Athlon 64 FX-62, while the supercharged Core 2 Extreme X6800 established a new performance tier at the high-end. Further, it did so at reasonable power levels, finally taking the efficiency fight back to AMD.

Intel doubled down, literally, with the Core 2 Extreme QX6700 at the end of 2006. Although Intel had introduced a four-thread processor previously, the Core 2 Extreme QX6700 was the first CPU with four cores to hit the market. It took two dual-core dies from Core 2 Duo and put them together on a single package. AMD brute-forced a quad-core with the 4x4 platform and dual Athlon 64 FX-70 chips, but there was a major tradeoff in cost, thermals, and power demands.

The coast of Nehalem (2007 - 2010)

The coast of Nehalem (2007 - 2010)

For the first time in the early aughts, Intel was firmly in the driver’s seat for enthusiasts. AMD drummed up some interest with its dual-chip Athlon 64 systems, and it finally moved down to a 65nm node at the start of 2007. But Intel was on a tear, and it would continue its momentum for years to come.

That started by formalizing the success of the Core microarchitecture. Instead of squeezing everything out of a microarchitecture for several generations, as it had done with P6 and NetBurst, Intel transitioned to its well-known tick-tock cycle. First, there’s a node shrink on its existing architecture, then there’s a new microarchitecture on that node, and the cycle continues. Core was the tock at 65nm, and it would move down to Penryn revision at 45nm later in 2007.

AMD struggled to keep pace. After introducing its AM2 socket in 2006, it continued refining the Athlon 64 X2 lineup with a new 65nm node, but Intel was firmly in the lead, forcing AMD to slash prices and settle into the market as a budget-focused alternative to the shiny Core 2 Duos. AMD doubled down in this area with its K8 microarchitecture, releasing a series of efficient “BE” series chips throughout the back half of 2007, which we found were excellent for efficiency and price-to-performance in our review.

Team Red had its chips on K10, and specifically, the new Phenom brand that it made noise about throughout 2006 and 2007. The Phenom X4 series launched in November, featuring the first true quad-core design; that is, using a monolithic die as opposed to MCM like Intel’s Core 2 Quad. Unlike Intel’s Core 2 Extreme, which was reserved for only the most entrenched enthusiasts, AMD targeted midrange builders.

In our Phenom 9700 review, we found that Intel still maintained the performance crown, but AMD offered a cheaper quad-core and offered identical price-to-performance at release. Further, AMD offered support for the chips on both the AM2 socket and the new AM2+ socket, starting a trend of socket longevity that we can still see in action today. With cheaper quad-core CPUs and less upgrade cost, AMD focused less on battling Intel at the high-end and more on delivering in the midrange.

Intel continued to release more Core 2 Duo and Core 2 Quad models throughout 2008, but behind the scenes, it was working on its next major architectural shift: Nehalem. AMD built out its Phenom line, meanwhile, introducing a tri-core variant, as well as several “Black Edition” models that featured peak clocks and unlocked multipliers for enthusiasts, likely in a bid to grab some attention from Intel’s Extreme lineup.

Nealem came onto the scene in late 2008 in the form of Bloomfield chips. They required an entirely new platform and DDR3 memory, but also promised entirely new performance benefits. Intel managed to create a true quad-core chip with Bloomfield, and one that enthusiasts could actually afford, with the range going down as low as $280. Further, it reintroduced Hyper-Threading after ditching the technology during the early dual-core days, giving enthusiasts eight threads to play with.

The spread between Intel and AMD grew wider. In our review of the Core i7-965 Extreme, we found it was 64% faster than AMD’s fastest chip at the time. Despite offering compelling products at competitive prices, AMD was falling further behind. Intel was far ahead; it had a die shrink ahead, and the legendary Sandy Bridge microarchitecture was waiting in the wings to pick up the tick-tock cycle once again.

AMD bit back in early 2009 with Phenom II (along with Athlon II), finally moving down to 45nm. It brought Team Red back up in the rankings, but Bloomfield still held onto top-end performance. In our original Phemon II review, we found that Intel was about 22% ahead of AMD at the high-end, but AMD offered compelling performance given the platform costs. Sounds familiar.

With tight integration of design and manufacturing under one roof, Intel was moving faster than AMD on process improvements, allowing it to keep a consistent lead in performance, particularly at the high-end. Intel had its Lynnfield chips at 45nm, as well as Clarkdale chips at 32nm, but the 32nm successor to Bloomfield came in early 2010, known as Gulftown. And with Gulftown, Intel could claim a multi-core milestone on a monolithic die for the first time with the six-core Core i7-980X.

At $1,000, the Core i7-980X still only appealed to a small number of enthusiasts. AMD helped fill the gap later in the year with the Phenom X6 launch, introducing six-core models of its own. AMD couldn’t match the 980X at the high-end, but Phenom represented an affordable entry-point to six-core chips if you ran heavily-threaded workloads, as we noted in our review. Still, Phenom X6 was AMD trying to keep pace with Intel. Behind the scenes, AMD was working on a new microarchitecture called Bulldozer, which was built from the ground up for a new generation of chips and finally allowed AMD to move down to 32nm.

Bulldozer bulldozes world records, thermals (2010 - 2013)

Bulldozer bulldozes world records, thermals (2010 - 2013)

It’s easy to pick on Bulldozer in hindsight, but leading up to release, the anticipation was palpable. K8 was a smash success, and K10 built on that success, but Bulldozer was built from the ground up, presumably for the position AMD had found itself in the market. Nearly a year before Bulldozer showed up on the market, however, Intel introduced an architecture that still resonates among enthusiasts today — Sandy Bridge.

Intel unified its product stack with Sandy Bridge and set much of the foundation for the company’s releases through Raptor Lake Refresh. Instead of two broad ranges, Intel placed most of the Sandy Bridge lineup on a single socket. It also brought integrated graphics to all the chips in the lineup, at least in the initial range (some later releases cut the iGPU), as well as unlocked the multiplier on some non-Extreme SKUs to compete with AMD’s unlocked Black Edition chips.

It was a smash success. Reviewing four Sandy Bridge chips, our reviewer Chris Angelini wrote: “Existing Lynnfield- and Clarkdale-based processors already offer strong performance compared to AMD’s lineup. Significant gains, clock-for-clock, compound in the face of notable frequency increases across the board (thanks to a mature 32 nm process), giving Sandy Bridge an even more commanding position.”

Raw performance improvements are one thing, but Sandy Bridge was attractive for several other reasons, as well. Overclocking still represented a solid performance boost in this era, and Intel was offering overclocking capabilities at mainstream price points alongside chart-topping performance out of the box. They also introduced Quick Sync to accelerate video encode/decode, and although we have video encode/decode acceleration in modern GPUs, Quick Sync still serves as a fundamental feature for video editing and media servers.

AMD’s response was Bulldozer, which was rumored ahead of release to outperform Intel’s Core i7-950 by upwards of 50%, as well as introduce a true eight-core chip to the consumer market for the first time. If that wasn’t enough, prior to release, the flagship FX-8150 set a world record for clock speed, peaking at 8.429 GHz. AMD would be the first to release a consumer CPU with eight cores, but just about every other aspect of Bulldozer was problematic.

Achieving eight cores in a single package came with significant trade-offs. Up to this point, AMD hadn’t used any form of simultaneous multithreading, but it implemented a version of SMT in Bulldozer. Unlike Intel’s traditional SMT implementation, Bulldozer used two integer units on a core, but shared floating point resources. The major trade-off was how small the integer execution clusters were in order to save space. AMD designed an architecture for a world of heavily-threaded software that just didn’t exist at the time, and it traded very important single-core speeds to achieve that design.

The flagship FX-8150 was marketed as an eight-core chip, with the eight-core count coming from AMD’s odd SMT implementation. Although there were two integer execution units per “module,” as AMD calls them, the floating point unit was shared. This discrepancy was actually the focal point of a 2015 lawsuit, which AMD settled in 2019 to the tune of over $12 million.

It was a flop. Angelini sums up the issue nicely in his October 2011 review of the FX-8150: “[Intel doesn’t] have to do anything at all. Its nearly year-old 95 W parts fend for themselves without even a price adjustment.” Intel had new chips of its own, as well. Just six months later, it introduced Ivy Bridge, taking the solid foundation of Sandy Bridge and moving it down to a 22nm node.

Ivy Bridge wasn’t a big hit on desktop, but it didn’t need to be, given the advantage Intel had already established with Sandy Bridge. Improvements were in the single digits, as we noted in our Core i7-3770K review, but Ivy Bridge brought improvements to integrated graphics to fight against AMD’s burgeoning lineup of APUs and thermal improvements targeting small form factor devices — especially laptops in a new category of “ultrabooks” that Intel was targeting.

12 months after the FX-8150 was introduced, AMD released a revision of the Bulldozer architecture named Piledriver. It promised better IPC and higher clock speeds, which was compelling, as AMD’s FX-4170 released earlier in the year as the first CPU to hit 4 GHz out of the box. Piledriver had a test run earlier in the year through AMD’s Trinity APUs, as well, showing around a 15% improvement compared to Bulldozer.

The flagship Piledriver, the FX-8350, was indeed better than its Bulldozer predecessor, but it was clear the underlying architecture had issues that wouldn’t allow AMD to scale up. AMD’s flagship was only competitive with Intel’s Core i5 options, and power use, although tamed in Piledriver, still meant the chip ran hot. It was immediately forced into a price cut upon release. After two failures to launch flagships, Intel effectively owned the high-end, which it continued to dominate with CPUs like the Core i7-3970X.

Around six months after Piledriver chips shipped, AMD released another two chips, both running at an insane 220W TDP and shipping with their own liquid cooling system. The highest-end offering, the FX-9590, was the first CPU to hit 5 GHz out of the box. AMD had learned the hard way what it had preached back in the Athlon XP days — clock speed isn’t everything.

The dawn of 14nm (2014 - 2016)

The dawn of 14nm (2014 - 2016)

With a 22nm product shipped, Intel went back to a tock and came out the other side with Haswell. Today, Haswell is heralded as a legendary architecture; we’ve all seen forum comments about gaming with a Core i7-4770K more than a decade after it was released. At the time, however, it established a narrative that would follow Intel for the next several years. That narrative being that Intel ships a new generation of quad-cores, each year, with minor IPC improvements and not much more. That’s certainly the impression Angelini came away with after reviewing the Core i7-4770K.

Intel didn’t have to move the needle beyond that point. Although AMD had shipped Bulldozer and Piledriver, a lot of turmoil was going on behind the scenes. Two further revisions of Bulldozer, Steamroller, and Excavator were planned, but AMD largely canceled the two revisions outside of a few low-end products. During this time, AMD underwent a series of sweeping layoffs and executive changes, cutting thousands of employees. Looking back at the time through a modern lens, some long-time AMD employees say that the company would’ve faced bankruptcy had it not been for semi-custom partnerships with Microsoft and Sony for their game consoles.

From the release of Piledriver in late 2012 through 2017, AMD didn’t release a ton of new CPUs. It released some revisions of Piledriver chips like the FX-8370, but we didn’t see any new microarchitecture. And planned node shrinks with Steamroller and Excavator were canned, with only a handful of desktop CPUs surviving, which were repurposed as low-end Athlon X4 CPUs years later. Intel had won.

It didn’t immediately rest on its laurels, however. Hearing the criticism of Haswell for desktop enthusiasts, Intel introduced the Core i7-4790K alongside other ‘Devil’s Canyon’ chips in mid-2014 as it worked on another tick behind the scenes down to 14nm. The result, which arrived almost a year to the day after Devil’s Canyon, was Broadwell. The Broadwell-H range — not Broadwell-E, which shows up later — isn’t very big and didn’t have much for enthusiasts. But Broadwell got Intel down to 14nm, and it would stay there until the release of Alder Lake CPUs in 2021.

We didn’t know that at the time, though. Broadwell laid the 14nm foundation for Skylake, which came hot on the heels of Broadwell-H after that architecture experienced a series of delays. Intel’s first true eight-core chip, the Core i7-5960X from the Haswell-E range, still gave the HEDT market what they were looking for, but Skylake was pushing ahead in the mainstream. In early performance testing, we said Skylake was the first architecture “to really get enthusiasts excited since Sandy Bridge.”

Intel didn’t need to rush at the time, so it didn’t. There wasn’t an Athlon 64 breathing down Team Blue’s neck. A year later, in 2016, Intel launched Broadwell-E for HEDT, marking the first-ever 10-core desktop CPU with the Core i7-6950X. It wasn’t a massive leap forward over Haswell-E, but Intel was competing with itself. “Intel’s clearly the prettiest girl in the room, is well aware of this fact and, based on Broadwell-E's pricing, doesn't need to beat the ‘value’ of last generation's -Es by much,” our reviewer Igor Wallossek wrote in his Broadwell-E review.

Although Intel was a clear market leader, it was slowing down significantly. Earlier in 2016, it quietly revised its tick-tock cycle, moving to a tick-tock-tock cadence where we’d see a new process followed by a new microarchitecture followed by an optimization of that architecture. Intel wasn’t juiced up with Moore’s Law like it was in the early aughts, but it competed in a category of one. What were you going to do? Buy AMD?

Feeling Zen (2017 - 2020)

Feeling Zen (2017 - 2020)

Shortly after the ball dropped into 2017, Intel released its Kaby Lake range of CPUs, now sporting the “14nm+” process and serving as the first optimization pass in Intel’s new release cadence. It was fine. The range came with a clock speed bump over Skylake, but otherwise, Intel released the same architecture sporting nearly identical specs, from core counts to cache sizes.

Behind the scenes, trouble was brewing. Six months before Kaby Lake made its way to market, AMD detailed its first entirely new microarchitecture since Bulldozer, named Zen. In addition to promising a 40% improvement in IPC over Excavator, the Zen platform would come with support for DDR4 and finally move AMD down to a 14nm node. For the architecture itself, AMD implemented SMT, completely redesigned its cache hierarchy, and added a micro-op cache to aid an updated branch predictor.

Two months after Kaby Lake rolled out, AMD launched the Ryzen 7 1800X. The revolution didn’t happen in a day. In our Ryzen 7 1800X review, reviewer Paul Alcorn (now Tom’s Hardware editor-in-chief) wrote: “AMD's Ryzen 7 launch represents more than just a new CPU family. For most of our readers, it signals the return of competition to the enthusiast-oriented processor market. And considering the flagship 1800X’s potent cost advantage compared to Intel's Core i7-6900K… Ryzen 7 does deliver. It's just not as universally superior as the company wanted everyone to believe.”

AMD still had quite the year ahead. A month later, the Ryzen 5 1600X launched with performance that could rival Broadwell-E, just for a much cheaper price. And by Summer, the Ryzen 3 1300X proved you didn’t need an expensive CPU and motherboard to get into overclocking. AMD capped its Ryzen rollout with Threadripper, scaling up the Zen microarchitecture to massive core arrays and finally bringing something to the HEDT market — a market that Intel had almost wholly owned since the Pentium 4 days.

Still, Zen had shortcomings, particularly in games, where just about any quad-core from Intel still ruled the roost. AMD was competitive, but Intel was still firmly in the driver’s seat. It barely reacted to the Ryzen onslaught over the summer, rolling out its high-end Skylake-X and Kaby Lake-X HEDT offerings throughout the back half of 2017. Even then, however, problems started emerging.

Kaby Lake-X was effectively a rerelease of Kaby Lake with a bit of extra headroom, but restricted to the expensive X299 platform. It was discontinued less than a year after release. Skylake-X was Intel’s true next-gen HEDT offering, signaled by the first use of “Core i9” in front of its flagship SKU. It performed like an Extreme Edition, and it was priced like one too, despite an issue in thermal dissipation that we uncovered in our Core i9-7900X review. Meanwhile, AMD was rapid-firing firmware and chipset updates for its small Ryzen range, and fixing several issues that came up in reviews in the process.

Less than a year after Kaby Lake launched, Intel released Coffee Lake, which was yet another Skylake revision built on 14nm, but this time with extra cores in tow. As you can read in our Core i7-8700K review, Coffee Lake did what Intel wanted it to do, shoring up the fight in heavily-threaded productivity applications against AMD while maintaining leadership in games. Still, AMD was making headway. By the end of 2017, estimates suggest AMD took back anywhere from 2% to 12% market share from Intel, with the higher end of the spectrum coming mainly from the DIY PC market. That’s no small feat for a company that was dead in the water with CPUs 12 months earlier.

Back on more even footing, the next goal post was a node shrink. Intel was gunning for 10nm, which is a milestone it failed to meet with both Kaby Lake and Coffee Lake. AMD, as a fabless designer, was at the mercy of its then-partner GlobalFoundries for the next node shrink. AMD struck first with Ryzen 2000 in early 2018, built on GlobalFoundries 12LP node, which was a revision of the 14LP (14nm) node used in the original Zen. Fittingly, AMD called it Zen+.

Debuting the architecture was the Ryzen 7 2700X, which was an iterative update. However, it helped reacquaint the market with the progress AMD had made. Zen+ came with higher frequencies and reduced memory latency, and all of the software adjustments AMD had made after the original Zen launch. And the range seemed specifically designed to undermine Intel, offering overclocking support across the full stack (and with B-series chipsets), and bundling a surprisingly decent cooler in the box.

Intel still held the edge in gaming, but the margins were narrowing, especially with a bit of overclocking thrown into the mix. Intel was feeling the heat, due in no small part to its continued issues moving down to 10nm. It responded in late 2018 with Coffee Lake Refresh, bringing the Core i9 branding into its main lineup for the first time with the Core i9-9900K and offering an eight-core, 16-thread chip. The strategy, it seems, was to push out AMD at the high-end, as Ryzen 7 was closing in on Core i7.

It worked. Intel had the fastest gaming processor on the market, and even the Core i7-9700K managed to push Intel’s lead in the Ryzen 7 battle higher. These marginal updates were buying time for AMD and Intel. Both companies clearly understood that whoever could go below 14nm first would have a massive advantage, and likely define an entirely new market dynamic.

AMD claimed that advantage for itself with the introduction of Zen 2 in mid-2019. Bolstered by TSMC’s 7nm node, AMD pushed out the Ryzen 9 3900X, moving beyond eight cores to AMD’s first 12-core consumer design. Intel held a slight edge in gaming through Coffee Lake Refresh, as you can read in our Ryzen 7 3800X review, but that delta was becoming less important as AMD took the lead in heavily-threaded workloads.

Later in the year, AMD rolled out the Ryzen 9 3950X, the first 16-core desktop processor ever. It was a bloodbath. Less than a year earlier, Intel had introduced its Skylake-X HEDT platform, including the Core i9-9980XE priced at $2,000. Now, at stock settings, the $750 Ryzen 9 3950X offered better multithreaded performance, along with competitive single-threaded and gaming performance. And you didn’t need to shell out for Intel’s expensive HEDT platform. And you could unlock PCIe 4.0, whereas Skylake-X (and even the following Cascade Lake-X) were locked to PCIe 3.0. You don’t spend top dollar on an HEDT platform for last-gen connectivity.

Intel was getting pushed into a corner, and it followed up less than six months later with Comet Lake to stave off AMD’s Ryzen onslaught. The flagship Core i9-10900K allowed Intel to maintain the lead in gaming, but now, AMD was in a clear lead in applications with the Ryzen 9 3950X.

Reviewing the Core i9-10900K, Alcorn wrote: “The Core i9-10900K is exactly what we would expect from an overclocked 10-core 14nm Skylake derivative: Exceptional performance in gaming and lightly-threaded workloads, competitive performance in multi-threaded work, and downright ugly power consumption and thermal output. And that's pretty much what you get with the Core i9-10900K – an overclocked 14nm processor right out of the box.”

AMD didn’t let up. It moved onto Zen 3 later in the year, launching its 16-core Ryzen 9 5950X alongside the main range in late 2020. And with its fourth Ryzen salvo launched, the battle was over. Opening our Ryzen 9 5950X review, Alcorn wrote, “With the Ryzen 5000 series, it's fair to say that AMD has finally, and fully, eclipsed Intel's performance dominance in desktop PCs.” It was a clean sweep, with AMD taking the lead in gaming, multithreaded, and single-threaded performance. Three years and four CPU generations later, AMD was back on top.

Forging a new path (2021 - 2024)

Forging a new path (2021 - 2024)

In the years leading up to 2021, it had become clear that a tick-tock, or even a tick-tock-tock, wasn’t possible any longer. Process shrinks were arriving later, and a pesky little pandemic threw the tight supply chain required for chip manufacturing into a frenzy. Both AMD and Intel knew they needed a different approach, but that would manifest in wildly different ways.

Intel was all-in on a hybrid architecture, using a mixture of microarchitectures on a single package to bolster core counts, similar to Arm-based designs. Intel talked a lot about Alder Lake leading into 2021, overshadowing its own launch of 11th-Gen Rocket Lake chips. The flagship Core i9-11900K was a massive disappointment, carrying all of the issues of the previous-gen Core i9-10900K while packing two fewer cores. Yes, Intel actually cut two cores from its flagship.

It seems Intel knew the issues with Rocket Lake. The chips launched with little to no fanfare, and as opposed to a gradual rollout like we see with most CPU generations, Intel blasted every model of Rocket Lake onto the market, knowing full well that Alder Lake chips would take their place eight months later. AMD, with renewed confidence, slowly built out the Zen 3 lineup with new APUs and variations of Ryzen 5000 as it worked on its next-gen Zen 4 architecture.

In late 2021, Intel swept Rocket Lake under the rug with the release of Alder Lake. Intel had finally moved on from 14nm with Intel 7 (10nm), and it was mostly successful. Intel reclaimed top placements in gaming, multithreaded, and single-threaded performance, and although the margins were thin, Alder Lake made it clear that Intel wouldn’t go quietly. “The Alder Lake processors mark a massive generational leap forward for Intel in nearly all facets, including gaming, performance in lightly- and heavily-threaded work, power consumption, overclocking, and platform connectivity options,” wrote Alcorn in our Core i9-12900K review.

AMD was working on something unique of its own, however. Zen 4 was in the oven, and it was clear there would be a competitive battle with Alder Lake. But before Zen 4 arrived, AMD introduced the Ryzen 7 5800X3D. It was the first processor with AMD’s 3D V-Cache packaging, and at the time, it looked like a slightly-tuned processor targeting gamers, with somewhere in the range of a 10% to 15% uplift in gaming performance specifically. In a surprising turn, the speculation actually undersold just how big of a deal the Ryzen 7 5800X3D would become.

Six months after the release of the Core i9-12900K, AMD was back on top of the gaming charts with the Ryzen 7 5800X3D, no less sporting a last-gen architecture and an SRAM stacking technique that limited boost clocks and locked the multiplier down. It outran the Core i9-12900K by nearly 10% in games while costing hundreds less, and it was nearly 30% faster than a stock Ryzen 7 5800X, as you can see in our Ryzen 7 5800X3D review.

Intel would come back with Raptor Lake in late 2022, but the Ryzen 7 5800X3D established a new category of true gaming CPUs that traded some application performance for peak frame rates. And that’s a category of chips that even today Intel hasn’t managed to crack.

AMD came first, however, launching Zen 4 in September 2022. The flagship Ryzen 9 7950X managed to leapfrog the Core i9-12900K, as you can see in our Ryzen 9 7950X review, but not by much, and the Ryzen 7 5800X3D remained at the top of the gaming charts. Immediately, speculation around 3D V-Cache chips for Zen 4 went into motion. Also tampering the Zen 4 release was an entirely new platform, which required costly DDR5 memory.

Intel capitalized with Raptor Lake mere weeks later. The flagship Core i9-13900K was back on top across tests, even managing to outclass the Ryzen 7 5800X3D in games. For the first time since the heyday of Athlon, we had a hotly competitive CPU market with AMD and Intel leapfrogging each other with each new release. Still, there was a niche that wasn’t being filled. 3D V-Cache disrupted the status quo for gaming processors, but it came with a significant trade-off to application performance. The stage was set for a CPU that could offer the best of both worlds.

AMD delivered that in early 2023 with the Ryzen 9 7950X3D and (to a much lesser degree) Ryzen 9 7900X3D. A couple months before, Intel cracked the 6 GHz barrier out of the box with the Core i9-13900KS, but AMD was offering something more compelling than peak clocks. The Ryzen 9 7950X3D managed to outclass Intel in multithreaded and single-threaded performance, all while offering a double-digit jump in gaming performance thanks to 3D V-Cache.

Raptor Lake saw a refresh later in 2023, and although the flagship was able to close the application performance gap in our Core i9-14900K review, AMD still held a firm grip on gaming performance, especially with the trimmed-down and relatively affordable Ryzen 7 7800X3D. AMD had taken the lead, but Intel, finally, executed its tick-tock-tock strategy and set its eyes on a radically new architecture in the form of Arrow Lake.

Reckoning with the real world (2024 - today)

Reckoning with the real world (2024 - today)

Under AMD’s thumb and clearly behind in pace, Intel needed to innovate. The result was Arrow Lake. Like Bulldozer, it’s easy to write Arrow Lake off in hindsight, especially given how recent it is. As you can read in our Core Ultra 9 285K review, Arrow Lake chips only marginally improved in application performance over their 14th-Gen counterparts, and they were actually slower across most games. But, architecturally, Arrow Lake is as big a swing as Bulldozer was.

For the first time, Intel outsourced manufacturing to TSMC, clearly behind the Taiwanese manufacturer for cutting-edge nodes. It disabled Hyper-Threading, killing off a staple of Intel CPUs for decades, and it doubled down on Intel’s hybrid architecture. Those bets didn’t pay off, but they were big bets for a company struggling to reckon with a reinvigorated AMD.

AMD followed up Zen 4, predictably, with Zen 5 in mid-2024, shortly before the Arrow Lake release. With Arrow Lakes' struggles, it’s easy to forget the problems Zen 5 had at launch, and the relatively small generational uplift it offers even today. AMD has continued to build out this lineup with X3D chips, and it finally delivered 3D V-Cache on both CCDs with the Ryzen 9 9950X3D2. But going back to our Ryzen 9 9950X review, Zen 5, at its core, isn’t the massive uplift we had become accustomed to in the early days of Zen.

Intel tried to give Arrow Lake a bit more life with a small refresh earlier this year in the form of the Core Ultra 7 270K Plus and Core Ultra 5 250K Plus, and those CPUs set the stage for the next era of CPUs. They put Intel into the position AMD found itself during the Bulldozer/Steamroller days, clearancing off silicon to maintain a competitive position in the market.

That’s where we are today, with our sights set on Zen 6 and Nova Lake. But there are some realities in the PC enthusiast space that we have to contend with today. DRAM pricing is out of control, and showing no signs of slowing down, and a sudden boost in demand for CPUs for agentic AI means consumer chips have taken a backseat. Zen 6 and Nova Lake were both expected by the end of the year; it’s looking more likely that they’ll slip into 2027.

History doesn’t repeat, but it often rhymes, and we can see traces of days past over the last 30 years start to creep into the dynamics today. Today, we see a defiant AMD and an Intel that seems ready to get scrappy in order to earn back market share. Will it pay off? We don’t know, but Tom’s Hardware will be here to cover whatever comes next in the world of CPUs, just as we’ve been for the past 30 years.

It has now been 30 years since our founder and namesake, Dr. Thomas Pabst, wrote the first articles that came to define Tom’s Hardware, focusing on providing unbiased, fact-based reporting backed by comprehensive testing, a mission that we strive to continue today. To celebrate our 30^th Anniversary, Tom’s Hardware is kicking off a series of articles that look back at the evolution of PC hardware and peripherals over the course of the last 30 years, with the first being a look at the evolution of the CPU. But before we dive into the history of CPUs and GPUs, let’s take a quick look back at the early history of Tom’s Hardware.

A then-practicing doctor and surgeon, Pabst began testing hardware in the early days of the desktop PC revolution, first publishing under the name of Tom’s Roadrunner Page in 1996, then rocketing the brand to fame after it evolved to become Tom’s Hardware Guide later that same year. In the early days, Pabst focused on testing motherboards and CPUs, but he also began testing graphics cards with the Nvidia Riva 128 being the first, followed by others like the 3Dfx Voodoo, among many, and he even penned a custom benchmark that was billed as the world’s first real-world 3D benchmark. Those foundational categories still live on today in our coverage.

Pabst’s biggest breakthrough came when he published an unsanctioned pre-release review of an Intel Pentium II CPU that he acquired from friends in the publishing business, who also published reviews. Naturally, Intel wasn’t fond of the resulting negative coverage, and the firm threatened to pull ads from two of the publications involved if the reviews weren’t removed. The ensuing spat garnered widespread coverage, with the conflict making it into the pages of the New York Times and other mainstream news outlets. Intel admitted to using its advertising contracts to threaten the sites and apologized, and the issue thrust the Germany-based Tom’s Hardware into the spotlight on the international stage right as CeBIT 1997 began, where Pabst met many of the industry contacts that helped move the site forward.

A few years later, Pabst discovered persistent bugs with the Intel Pentium III, some of which he exposed in Linux, which wasn’t commonly used for benchmarking at the time. Pabst refused to surrender his sample to Intel, saying it was his only proof of the issue. Due to the bugs Pabst discovered, Intel eventually pulled the processors from the market until a new chip stepping could be developed. Intel then excluded Pabst from coverage of the Pentium 4, which he viewed as another retaliation, sparking another very public conflict that cemented the brand's reputation for uncompromising independent journalism.

Tom’s Hardware Guide evolved over the intervening 30 years, spreading into new categories like networking and news coverage, eventually becoming known as Tom's Hardware — though it is still easy to spot our veteran readers because they still refer to the site as ‘THG.’ Pabst sold the site in 2007 to Best of Media Group and served as Chairman until 2008. Our sister site, Tom’s Guide, was born in 2007, and Tom’s Hardware has also branched out with multiple non-English licensees of the brand over the years, with Tom’s Hardware France and Tom’s Hardware Italy still operating to this day. Tom's Hardware was acquired by our current publisher, Future plc, in 2018.

PC building certainly looks a lot different today than it did when Pabst first began testing PC hardware. Back in those early days of the PC, things such as user-friendly BIOS tuning didn’t exist; enthusiasts simply adjusted jumpers and DIP switches to fine-tune their systems, paving the way for the overclockers of today with skill and a determination to wring more performance out of their systems. That spirit lives on in our coverage and in our vibrant community of enthusiasts.

You’ll see constant references to our past in our valued forums, where thousands of enthusiasts, from newcomers to veterans of 20 years or more (many who still remember setting DIP switches by hand), help the community solve vexing issues with their tech while also providing valuable insight and commentary on the latest happenings in the tech sphere.

Today, our ethos remains the same — we strive to deliver unbiased coverage of the latest technology, backed by comprehensive benchmarking to underline our conclusions, thus delivering the best possible buying advice to our readers. We now cover the full breadth of PC components and peripherals while continuing to branch out into new areas that resonate with our audience, such as 3D printing and associated products, but we’ll always remain grounded in our core areas of PCs and PC components.

Despite newfound challenges facing the publishing business, such as the rise of AI that lifts our expertise without compensation — and often without attribution — and an ever-more punishing Google landscape, we work tirelessly to stay on our current growth trajectory while developing additional new means to serve our readers, such as our Tom’s Hardware Premium service. This subscription-based service provides our readers with longer-form news, analysis, testing, and features for those who want to dig even deeper into our core coverage areas. Our service also includes access to our Bench database, which provides up-to-date benchmarks of the latest PC hardware in an easy-to-compare format.

The silicon, software, and publishing landscape have all changed dramatically over the last three decades, but our goals haven’t shifted, and yes, we still carry on with many of our old traditions. We thank you, the readers, for providing us with the opportunity to share our passion for hardware with you for the last thirty years, and invite you to join us for the next 30.

An intrepid TechTuber has tested a trio of passive mini PCs from the Subway sandwich chain to check if they can be repurposed for gaming fun. In a recent video, Garkus indicates that the three Intel Skylake-powered mini PCs that had been displaying sandwich menus above the serving counters for a decade but were saved from scrap/landfill, alongside a matching set of LG digital signage TVs. Spoiler: they are too puny for mainstream AAA gaming in 2026, even after doubling the RAM installed.

Before getting on with the digital signage-to-gaming conversion, Garkus investigated the hardware in hand. Labeling indicated that the three slim mini PCs were all Advantech DS-081 models (official PDF link). Pondering over that data sheet, we see that the variant with the Intel Core i3 6100U, as these were, carries the full designation of DS-081GB-U21A1E.

The processor is now both long in the tooth and low powered, so immediately we know this 2C/4T @ 2.3 GHz CPU, configured to suck between 7.5W and 15W, won’t be ideal for modern AAA titles. Moreover, the iGPU is the Intel HD Graphics 520 with 24 EUs and clocks up to just 1.00 GHz, sharing the DDR4 system RAM.

A DS-081GB-U2A1E is quite expandable for such a small, low-powered set-it-and-forget-it unit. It has twin HDMI 1.4, twin Ethernet, four USB 3, audio in/out, and an RS-232 serial port accessible from the outside. Inside, users can configure the machine via twin DDR4-2133 SODIMM slots (up to 32GB total), a SATA III HDD/SSD, and an mSATA port that looked like it was an M.2 2242 slot in the video. This passive machine is designed to run signage 24/7 in environments with 0 ~ 40° C (32 ~ 104 ° F) ambient temperatures.

Setup and gaming

These systems were found to actually come with just 4GB of RAM (one slot used) and with a 64GB SATA SSD installed. They booted to Windows and went straight to kiosk mode, displaying the Subway sandwich menu. We saw an extra 4GB DDR4 stick added to bring the test system(s) up to 8GB RAM in total.

After a bit of OS wrangling, Garkus decided to set up the salvaged trio of passive mini PCs as follows. One kept Windows 10, another got Bazzite Linux (because SteamOS balked at the SATA-only storage), then another went Hackintosh with macOS Monterey installed.

Gaming tests began with a very light test. The system ran Peggle, and this 2D puzzler posed no problems. After this modest victory, Garkus ambitiously leapt straight to GTA V. This legendary but now older title could only reach a frame rate of about 15 fps. But it was found to have defaulted to high settings, took ages to get ready to run on Bazzite, then crashed on exit.

Probably not following best benchmarking practice, the tech tinkerer appears to have decided to test Mario Kart Wii emulation performance while GTA V was still compiling shaders… Later, a test run in Minecraft delivered a wildly inconsistent but roughly 25 fps performance. As is now established as the Garkus testing MO, resolution, quality settings, and so on weren’t shared.

To conclude the gaming part of the video, the TechTuber suggests that these ex-kiosk machines are probably best suited to emulating older consoles up to the PS2 and original Xbox era. We think that for PS2 emulation, you will still need to restrict yourself to lighter titles and reduced settings for smooth action.

After granting about a dozen manufacturing licenses to make various x86 CPUs back in the 1980s, Intel ceased to license both its cores and instruction set architecture (ISA) in a bid not to create rivals. However, in an unusual turn of events, Intel has quietly granted startup RosaicLabs access to its Atom processor technology, reports Reuters. The company was incorporated in May and is led by Lip-Bu Tan's co-investor.

Intel provided Rosaic access to an unknown Atom-class core, which enables the company to build its own custom processors based on x86 general-purpose cores, according to the report. The renowned chipmaker plans to ship Rosaic register-transfer level (RTL) code ​for the Atom processor core, which will let the startup build its custom system-on-chip (SoC) both at Intel Foundry and elsewhere.

The startup is reportedly led by Amarjit Gill, a venture capital investor who partnered with Intel's CEO, Lip-Bu Tan, on multiple occasions in the past. The two invested in such companies as Nuvia and Rivos, which were later acquired by Qualcomm and Meta, respectively.

RosaicLabs does not have a website or a LinkedIn profile, which is common for startups when they operate in stealth mode. The company was incorporated in May and is currently seeking a seed funding round of $10 million, according to a document seen by Reuters.

Since RosaicLabs does not have a website or a LinkedIn profile, it is completely unknown what kind of SoC it plans to develop and which markets it is going to pursue. One could imagine that it is in Intel's interests to license technology to companies that seek to address markets which Intel has no plans to address.

Arguably the biggest question is which Atom-class core Intel licensed to Rosaic. Traditionally, Atom cores were developed for inexpensive low-power devices, applications that Intel ceased to address about a decade ago. Since then, the low-power x86 architecture has been used to build custom SoCs for telecom and adjacent applications, embedded CPUs, efficiency (E) cores for client CPUs, and more recently cloud-optimized Xeon processors. Intel's most advanced low-power x86 cores to date are Crestmont, which powers Xeon 6700E-series CPUs, Skymont, which is used in Core Ultra 2-series CPUs, and Darkmont, which powers Xeon 6+ CPUs.

Skymont and Darkmont feature a 9-wide decode, 8-wide out-of-order engine, and 16-wide retire, which makes them fairly capable cores that wed high performance potential with energy efficiency. Meanwhile, Darkmont is optimized for data center workloads, so it has better branch prediction, improved prefetch, an enhanced vector engine, and higher L2 bandwidth. By contrast, Crestmont features a 6-wide decode and an 8-wide retire, which puts it well behind the newer cores.

If Intel gives Rosaic complete, synthesizable RTL of an Atom-class core, Rosaic could technically modify the core at several levels, including changing cache sizes, reorganizing the pipeline, increasing clocks, and altering power-management logic, just to name a few options. However, this does not automatically mean Rosaic has unrestricted rights to enhance Intel's technology, as the company could provide RTL under various conditions with numerous restrictions. After all, it does not want to create a competitor for itself. Still, we do not know the terms of the license.

Intel granted about a dozen manufacturing licenses to build its 80286 and 80386 CPUs in the 1980s to various chipmakers in a bid to provide chipmakers with second sources for its processors and expand usage of its x86 ISA. However, only AMD got an actual x86 license that allowed it to build x86 CPUs of its own designs.

After disposing of its StrongArm/XScale business to Marvell in 2006, Intel witnessed the smartphone revolution essentially empty-handed as its Atom processors could not compete with highly integrated Arm-based SoCs in handsets. Intel tried to expand the reach of its low-power Atom CPU cores in 2009, so it signed a memorandum of understanding with TSMC and planned to port its Atom cores to a TSMC node and enable TSMC clients to integrate that hard IP into their processors.

That initiative has never taken off, so eventually Intel kicked off its SoFIA (Smart or Feature Phone on Intel Architecture) joint SoC development program that enabled third parties to use Intel Atom cores and modem technology (implemented using TSMC's 28nm node) in their application processors for handsets. While both Rockchip and Spreadtrum eventually came up with their SoFIA 3G and SoFIA 4G SoCs based on Airmont cores and made on TSMC's 28nm technology, both processors were released in 2015, had to compete against SoCs made on Samsung's 14nm-class node or TSMC's 16FFC node, and never got popular. Ultimately, Intel produced an eight-core Spreadtrum SoC at its fabs using its 14nm manufacturing technology, but that processor also failed on the market.

As a result, Intel licensing a CPU core to a third party is a very rare occurrence these days and the first in this decade. The reasons behind the move are completely unclear because the RosaicLabs startup is two months old, it cannot pay Intel cash, and its commercial prospects are completely unclear. While one may argue that now that Rosaic has access to x86 cores, it is not going to pursue Arm or RISC-V cores, keeping in mind that hundreds of startups choose Arm or RISC-V every year, addressing one startup does not enable Intel to expand its x86 share compared to Arm or RISC-V tangibly.

In any case, for now, the deal between Intel and RosaicLabs leaves more questions than answers, mainly because all we know about RosaicLabs is that it is led by an old acquittance of Intel's chief exec, Lip-Bu Tan.

Intel Foundry says that it has completed RAMP-C, the United States government program awarded to the company in 2021 to stand up a secure, domestic leading-edge chip ecosystem on its 18A process. The program funneled money to commercial and defense partners to run test chips on a design kit that wasn't finished yet, and its conclusion marks readiness for external customers who will pay full price to fabricate real products, including those who might use the Intel Secure Enclave manufacturing flow that RAMP-C helped to shape.

The announcement doesn't name any customers that Intel may have secured as a result of RAMP-C, although the program roster has been public for years and includes Nvidia, Microsoft, IBM, Qualcomm, Boeing, and Northrop Grumman. That may be down to the sensitive nature of any actual defense industrial base (DIB) products that are likely to be produced with the Secure Enclave defense-focused manufacturing flow for those products, which spans project stages from design to chip fabrication to advanced packaging.

Intel says RAMP-C was one of the programs that influenced Secure Enclave, and having a number of potential DIB customers run and test prototypes on 18A through likely generated valuable knowledge for Intel, the U.S. government, and its partners as those stakeholders work together to create a defense-ready domestic chip source.

Stu Pann, then SVP and GM of Intel Foundry Services, told Tom's Hardware back in February 2024 that the program's announced partners were IBM, Microsoft, and Nvidia, and that all three were running test chips paid for by RAMP-C. The funding let them "operate with immature PDKs, which normally they wouldn't do," Pann said, and covered their associated costs. Intel got PPAC data in return: how prospective customers rated 18A on power, performance, area, and cost.

Intel disclosed the roster in stages rather than all at once. Nvidia, Qualcomm, Microsoft, and IBM were named across the first two phases, Boeing and Northrop Grumman joined in July 2023, and Trusted Semiconductor Solutions and Reliable MicroSystems came in under a third phase that Intel says was awarded in April 2024.

Nvidia's participation runs back to the program's early phases, four years before it agreed to buy $5 billion of Intel common stock in September 2025, a deal that closed in December at $23.28 per share for more than 217.4 million shares. That agreement covers custom x86 CPUs and RTX SoCs, and carries no commitment to manufacture Nvidia silicon at Intel.

Secure Enclave, the follow-on program Intel references, is worth up to $3 billion and was finalized alongside the company's $7.86 billion CHIPS Act award in November 2024. Congress required that CHIPS money pay for it, which is why the commercial grant is smaller than the $8.5 billion originally proposed.

Intel Foundry booked $293 million in external revenue last quarter against $5.8 billion in total segment revenue and a $2.1 billion operating loss, according to the company's Q2 2026 financial results. Fortinet, named last week as the first publicly disclosed external foundry customer under CEO Lip-Bu Tan, is building its security processor on Intel 4 rather than 18A. On the same earnings call, Intel committed to 14A high-volume manufacturing in 2028.

Today marks 20 years since the first raft of Intel Core 2 Duo processors, codename Conroe, was launched. Ten Intel Core 2 Duo and Intel Core 2 Extreme processors were unveiled for consumer and business desktop and laptop PCs and workstations on July 27, 2006. We were lucky enough to test Intel’s now legendary new desktop processors earlier in the month, and our reviewer anointed the Core 2 Duo “the new king.” Our early hands-on review underlined that “as soon as Core 2 Duo hits the market, it will outperform the complete Athlon 64 family (X2 and FX) in all areas, including gaming, where AMD has traditionally been very strong.”

The GHz race ends with an architectural revolution

One of the defining characteristics of the first Intel Core 2 Duo chips was that they kicked the GHz race to the periphery of the battlefield. After years of chips being sold with this performance statistic placed most prominently, Intel and the tech media had to educate the wider public that higher GHz numbers didn’t define performance.

Intel Conroe desktop chips came with a generational performance uplift we don’t see often. These third-generation dual-core processors from Team Blue would “provide up to a 40 percent increase in performance and are more than 40 percent more energy efficient versus Intel's previous best processor,” according to launch-day PR. Testers also observed that even the entry-level new Conroe chips could outpace the mighty flagship desktop Pentium Extreme Editions, despite running at nearly half the clock speed.

Behind the real-world performance successes Intel eagerly highlighted, and reviewers seemed genuinely excited by, there were a number of architectural innovations and refinements. Intel boasted that the Core 2 Duo contained “a whopping 291 million transistors” and had achieved many benchmark firsts in internal tests. Conroe arrived with higher efficiency, shorter pipelines, improved branch predictions, new shared Smart Cache, and substantially higher IPC, all built upon Intel’s newest 65nm process technology. With this attractive new price, it wasn’t difficult for Intel to retire its former king, with its hot, power-hungry, and big GHz Netburst architecture.

Defining the next decade+

With the Core 2 Duo, Intel regained its performance leadership from AMD and its Athlon parts. Conroe, the desktop Core 2 architecture, didn’t get singled out in our five best Intel CPUs of all time article (2024), but it was the direct ancestor of the legendary Core 2 Quad CPUs. These quad-core CPUs would take the Gillette-like next logical step with four cores on a chip, combining two Conroe dies in a single package, and launching in January 2007.

Moreover, from the mid 2000s onwards, multi-core became mainstream and developers seriously began to optimize applications and games for processors boasting more than just Core 0. Admittedly, single-threaded performance can still be important in Windows/apps/games in 2026.

To conclude, Intel’s Conroe would set the foundations for the firm’s CPU market dominance for more than a decade. Most would argue this successful run lasted all the way until the AMD Ryzen family matured and hit full stride with the Ryzen 3000 series.

Imperial Valley Computer Manufacturing has filed a lawsuit in a bid to gain access to Colorado River water, 287 million gallons of which it says it needs to cool a 330-megawatt data center, which would be the largest in the state. Despite only representing a fraction of the region's water supply, the buildout of the data center may affect the local farming and adjacent industries and terminate hundreds, if not thousands, of positions, reports Business Insider.

After two cities in the region denied the California-based AI data center recycled wastewater for cooling, it filed a lawsuit demanding to get water from the Colorado River for cooling. The 330-megawatt facility was not only designed to be the biggest AI data center in California, but it specifically committed not to use water from the Colorado River because it was promised wastewater. But now the owner of the data center is essentially asking to redirect water supply from agriculture to the facility.

Imperial Valley Computer Manufacturing — the owner of the 330 MW AI data center — is requesting access to approximately 287 million gallons of water per year after two cities — El Centro and Imperial — declined to supply reclaimed wastewater for cooling. The Imperial Irrigation District (IID), which distributes Colorado River water throughout Imperial Valley, also denied the company's request. The Colorado River supplies water to roughly 40 million people across seven western states and serves as the valley's sole freshwater source for roughly 180,000 people. Agriculture consumes about 80% of California's allocation from the river, while roughly 95–97% of the water IID delivers goes to agriculture.

The data center is seeking roughly 287 million gallons per year (about 750,000 gallons per day, or ~880 acre-feet per year), whereas the Imperial Irrigation District (IID) holds rights to approximately 3.1 million acre-feet of Colorado River water annually, which means that the data center demands only a small fraction — 0.028% — of IID's total water supply.

Sebastian Rucci, a Huntington Beach attorney who leads the project, claims that the facility's water consumption would be comparable to that of a 160-acre farm and will require no additional Colorado River allocation. In fact, he states that the facility would not increase pressure on the river because the company intends to purchase nearby farmland together with its associated water allocations.

Under the proposal, irrigation on those properties would cease, thus transferring the existing water quotas to be redirected to the data center cooling, at the expense of local farming output and associated jobs. "There's a lot of resistance in any agricultural community to 'buy and dry' because that's jobs," a senior fellow at the Pacific Institute focused on Colorado River Basin water use told the outlet. According to them, local resistance to the plan is less about the amount of water, and more about buying up farmland and reallocating it for industrial use.

The approach, of course, differs from the earlier plan that intended to avoid using Colorado River water altogether. However, after the data center was denied wastewater from two cities, it does not have a choice if it wants to go ahead with the buildout.

Rucci reportedly indicated that the project would provide substantial economic benefits for the local community, including 1,688 construction jobs, more than 100 permanent positions, and an estimated $2.95 billion in economic impact over 30 years. For a region where unemployment stood at approximately 17% in May, the economic diversification is essential. However, the big question is whether 100 permanent roles could offset the lost positions in the farming industry and industries tied to agriculture.

Water policy specialists interviewed by Business Insider said that the debate extends beyond the project's annual consumption. Instead, they questioned whether converting irrigated farmland into industrial use is an appropriate long-term direction for the region, which has historically depended on farming. The experts also warned that although landowners could benefit from selling land or water rights, surrounding rural communities may lose employment and business activity adjacent to agriculture, which includes equipment suppliers, repair shops, and sellers of fertilizers. Another factor mentioned by the experts was the U.S. reliance on farms around Imperial, California, and Yuma, Arizona, as they were the main suppliers of certain agricultural products in winter.

FPGA and embedded systems expert Adam Taylor has recreated the U.S. Navy’s F-14 Tomcat’s Central Air Data Computer (CADC) in an FPGA. The CADC is famous for being the brains behind the F14’s advanced fighter capabilities including the control of the aircraft’s signature articulated sweep-wing system. So, what better way to test the new FPGA than in a 3D printed scale model of the F-14 Tomcat? Check out the video embedded below.

We wrote about the F-14 Tomcat’s CADC last year after discussions erupted on social media about whether this flight computer was actually powered by the "world’s first microprocessor." The brains behind the CADC were provided by the MP944. This chip lived in the shadows for quite some time, though. Despite the MP944 microprocessor beginning service in June 1970, over a year before Intel’s legendary 4004 would become available (November 1971) it was an official secret until 1998. Thus, the Intel 4004 managed to steal the limelight from the true first microprocessor, say those in the MP944 camp.

To recap, the MP944 was a 20-bit, pipelined, parallel multi-microprocessor melded with state-of-the-art MOS technology and ran at 375 kHz, executing 9,375 instructions per second. The flight-system powering chip, designed by Steve Geller and Ray Holt and a 25-strong team, also passed stringent ruggedness tests and was capable of running in temperatures spanning -55 to +125 degrees Celsius.

The MP944 worked as part of a six-chip system in the CADC, for the real-time calculation of flight parameters such as altitude, airspeed, and Mach number – and was a key innovation to enable the Tomcat’s articulated sweep-wing system. So it had to be performant, and some chip architecture enthusiasts assert that the MP944 was actually “8x faster than the Intel 4004.” Remember though, the Intel chip was originally designed for a far more humble desktop calculator.

3D printed F14 swing wing test

Getting back to Adam Taylor’s recent achievement, and we now have a full open source set of VHDL source code, documentation, and testbenches for an FPGA recreation of the F‑14’s CADC. The GitHub repo says the FPGA used was a Spartan-7 based SoM, part of the Adiuvo Embedded System Tile. The resource isn’t just the MP944 logic, Taylor includes complete synthesizable VHDL implementations for all six original CADC chips.

Intel on Thursday published its financial results for the second quarter of 2026, posting revenue of $16.1 billion — a 25% rise year-over-year — amid high demand for client and data center products. The company also said that due to extraordinary demand for its own CPUs, it will initiate mass production using its 14A (1.4nm-class) fabrication technology in 2028, which is in line with TSMC's plans for its A14 process technology.

"With encouraging external customer progress and increased demand for our internal products, we remain on track for 14A risk production for our internal products in the second half of 2027, and we made the decision in Q2 to fully commit to high volume ramp in 2028," said Lip-Bu Tan, chief executive of Intel, during the company's earnings call with financial analysts and investors.

Typically, companies initiate high-volume manufacturing (HVM) using a new process technology about a year after initiating risk production. Assuming that Intel intends to start risk production using 14A in the second half of 2027, it is reasonable to expect the company to start 14A HVM in the second half of 2028. It remains to be seen whether by the 'second half' Intel means July or December. If Intel initiates high volume ramp in November or December 2028, actual products made using the technology will emerge in 2029. In any case, Intel typically begins manufacturing using its leading-edge nodes in its development fab in Oregon and while it formally calls it HVM, actual volumes produced at such fabs are relatively low.

Another thing to note about Intel's 14A is that in 2028 it will start making its own products using this process, not products from external customers. Apparently, Intel still does not have any external clients that have committed to use the technology to make their products.

TSMC typically initiates production using its latest nodes in December and usually calls it the 'second half of the year.' Assuming that it follows the same pattern with A14 (though the progress of the node can enable the company to pull mass production in provided that customers' designs are ready), then the volume ramp will occur in 2029. TSMC claims that multiple customers have already taped out their ICs on A14.

Intel reported a strong second quarter as its revenue reached $16.1 billion, up 25% year-over-year and $1.8 billion above the midpoint of its guidance. Formally, Intel's GAAP losses reached a whopping $11 billion. However, this was driven by the $13.619 billion of mark-to-market losses on Escrowed Shares related to Intel's CHIPS Act Secure Enclave agreement with the U.S. government. Meanwhile, the company's non-GAAP net income was $2.2 billion, which reflects profitable underlying operations. The company's GAAP gross margin increased to 40.1%, up from 27.5% in Q2 2025. Intel's Operating cash flow totaled $7.0 billion, prompting the company to raise its capital spending outlook for both 2026 and 2027 as AI-driven demand continues to exceed available supply.

Intel's Client Computing and Physical AI Group (CCPG) generated $8.9 billion in revenue, up 13% year-over-year. The company confirmed that the CCPG result was not driven by increased unit sales, but was a result of higher average selling prices (ASP) due to supply constraints.

"Client obviously exceeded expectations. I would say it was largely ASP, of which some of that was mix related, some of that was our own like-for-like changes in ASPs where we thought we had seen some inflation on our cost and needed to pass that on to the end customer," said David Zinsner, chief financial officer of Intel, during the call.

The Data Center and AI (DCAI) business delivered the strongest growth as its sales climbed 59% year-over-year to $6.3 billion amid surging demand for Xeon processors, expanding AI infrastructure deployments, and rapidly growing purpose-built silicon sales.

"Q2 year-over-year server growth was the strongest on record, Xeon 6 continue to be one of the fastest ramping products in Intel history, reflecting improving execution and strong customer demand," Tan said.

"We also continue to see strong momentum in our purpose-built silicon product line, with revenue up roughly 20% sequentially and nearly tripling year-over-year," Zinsner said. "Purpose-built silicon revenue nearly tripled year-over-year."

Intel Foundry posted $5.8 billion in revenue, an increase of 31% year-over-year, as Intel 18A production ramped. At the same time the production units losses dropped to $2.1 billion — down from $2.4 billion in the previous quarter and $3.2 billion in the same quarter a year ago. External foundry revenue reached $293 million.

"Intel Foundry operating loss in Q2 was $2.1 billion and $348 million better quarter-over-quarter as higher yields improved cycle times and increased factory scale across Intel 4, Intel 3, and 18A drove improved wafer costs," Zinsner said.

Intel guided its third-quarter revenue to $15.8 billion – $16.8 billion and a projected non-GAAP gross margin of 42% and an EPS of $0.38.

Intel and AMD are signing longer-term purchase commitments with Chinese server customers for data center processors, according to a new Reuters report that cites two people familiar with the talks. Prices for some server CPU products in China have climbed more than 40% since the start of the year and are still rising by over 10% month-on-month in some cases, one of the people said. Most of the agreements guarantee purchase volumes for about a year without fixing prices, and neither company responded to the publication's requests for comment.

Some customers have discussed commitments running two years or longer, one of the people told Reuters, with the deals covering unit volumes only, which leaves Chinese cloud providers and internet companies fully exposed to a market that has already added 40% to some CPU prices in under seven months. Memory makers struck similar long-term agreements with hyperscalers over the past year as AI demand consumed DRAM and NAND output, but those contracts typically trade a volume commitment for some pricing visibility. Buyers here get neither price protection nor, based on current lead times, fast delivery, but they do get a place in the queue.

Intel said in March that it was pursuing long-term agreements with potential customers as server CPU demand spiked, with CEO Lip-Bu Tan telling analysts on the company's April earnings call that demand "continues to run ahead of supply," singling out Xeon server parts. Tan also cited a multi-year supply deal with Google among several long-term contracts signed in the first quarter, so the model now spans U.S. hyperscalers and Chinese channel buyers alike.

Reuters first reported in February that Intel had warned Chinese customers of lead times stretching to six months on some server CPUs, with AMD quoting eight to 10 weeks. By late March, server makers told Nikkei Asia that average CPU lead times had blown out from one to two weeks to eight to 12 weeks and beyond. Intel CFO David Zinsner put a value on that in April, telling investors that unmet Xeon demand "starts with a B," and the company later confirmed price hikes on select consumer and server CPUs.

Agentic AI workloads are driving much of the demand, as inference and orchestration tasks pull server CPU-to-GPU ratios back toward parity. AMD, which is due to report earnings in early August, has raised its server CPU market forecast to more than $120 billion by 2030, based on the same trend.

Intel will report its second-quarter results later today, where the shortage and the durability of these commitments are likely to come up. Chinese buyers remain cut off from the most advanced AI accelerators under U.S. export controls, but Xeon and EPYC server CPUs carry no such restrictions, making them one of the few U.S.-made AI infrastructure components China can still purchase freely, if it can get them.

Intel will design, package, and fabricate Fortinet's sixth-generation Security Processor (SP6) on its Intel 4 node, the companies announced on July 21, giving the process its first named external foundry customer, roughly three years after it entered production. Intel told Tom's Hardware the agreement reflects "the strategy Intel outlined for Intel 4 several years ago," including support for custom networking ASIC workloads. Intel's own record from those years reads differently, however, with the company's 2021 roadmap having scoped Intel 4 to two internal products. And through 2022, it told engineers and investors that Intel 3, not Intel 4, would be its first process offered to foundry customers.

Intel 4's record

Intel's Accelerated announcement back in July 2021 said that Intel 4 would reach production readiness in the second half of 2022 for products shipping in 2023, naming "Meteor Lake for client and Granite Rapids for the data center." The release and its accompanying fact sheet, however, contained no reference to foundry customers, networking, or custom ASICs on the node.

At VLSI 2022, Intel disclosed that it wasn't building a high-density library for Intel 4 and that Intel 3 would be the first new node offered through what was then Intel Foundry Services. A 2024 post on Intel's own foundry blog describes Intel 3 as "Intel Foundry's first leading-edge process node," and Intel's fiscal year 2024 annual report listed the processes available to external customers as 18A, Intel 3, Intel 7, Intel 16, and a 12nm node co-developed with UMC. Intel 4 appears nowhere on that list.

Ericsson's RAN Compute processors, announced in November 2023, were built on Intel 4, so Fortinet's part won't be the first third-party silicon to come off the node. That work grew out of a bespoke Intel-Ericsson collaboration, though, and Ericsson's formal foundry agreement with Intel, announced in July 2023, covered 18A. Fortinet is the first named customer buying Intel 4 as a foundry service, and the first cybersecurity vendor on any Intel node. The Ericsson engagement is also the closest thing in the public record to networking silicon on Intel 4, two years after the strategy Intel now says it outlined for the node.

Fab 34 economics

Intel 4 entered high-volume manufacturing at Fab 34 in Leixlip, Ireland, in September 2023, producing the compute tile for Meteor Lake-based Core Ultra chips, and shares the fab with Intel 3. Intel sold a 49% stake in the facility to Apollo-managed funds for $11.2 billion in June 2024, then bought it back in April 2026 for $14.2 billion, funded with $7.7 billion in cash and $6.5 billion in new debt. That buyback returned 100% of Fab 34's wafer economics to Intel at a premium of roughly 27%, and it only pays off if the fab's EUV capacity stays loaded.

Meteor Lake is aging out of Intel's lineup as 18A-based Panther Lake ramps through 2026, which leaves open the question of what fills Intel 4 capacity next. A multi-generation firewall ASIC program is a reasonable answer with mature yields, a customer that values supply stability over bleeding-edge density, and a part Intel described as tailored for cost-sensitive applications. Intel said in April that yields were improving across Intel 4, Intel 3, and 18A.

Fortinet's supply chain

Fortinet's 2025 annual report names Renesas and Toshiba America as the contract manufacturers for its ASICs, utilizing foundries in Taiwan and Japan operated either by TSMC or by the contract manufacturers themselves. The current SP5, a monolithic 7nm Arm-based SoC announced in February 2023, sits in that supply chain, so SP6 on Intel 4 moves Fortinet's next flagship security processor out of a TSMC-linked flow and into Intel's. The disaggregated design language in the announcement points to a chiplet-based part, a first for Fortinet's SP line.

Fortinet re-engineered three FortiGate models in 2022, the 70F, 600F, and 3700F, to accept alternative components during the chip shortage, and CMO John Maddison told SDxCentral at the time that the company wouldn't wait for parts to arrive in 2023. The "resilient and diversified" supply chain used in the SP6 press tracks back to that experience. Ken Xie called Fortinet "the #1 firewall leader with a 55% unit market share" in the company's 2025 results in February, with approximately six million FortiGates deployed, so there’s real, substantial volume here even if the parts are relatively inexpensive.

Intel Foundry reported $307 million in external revenue for 2025, up from $159 million the year before, against total foundry revenue of $17.8 billion and an operating loss of $10.3 billion. External revenue in Q1 2026 was $174 million. Fortinet's hardware business runs at roughly 30% of its revenue, and, per analysis from ServeTheHome, SP6 is ultimately a component of a portion of an annual hardware stream around $2 billion, so the deal won't move Intel's foundry line materially, even at full production.

CEO Lip-Bu Tan told CNBC in May that he expected commitments from multiple foundry customers in the second half of 2026, and Intel told investors in January that two prospective customers were evaluating 14A test chips. The SP6 announcement comes inside Tan's stated window, and it finally gives Intel something its foundry marketing has lacked in a named customer with shipping volume on a node with mature yields. Meanwhile, an 18A or 14A commitment from a major external customer is still missing, and Fortinet's cost-sensitive parts on a 2023 node don't substitute for one.

Intel and Fortinet have announced a strategic collaboration to develop the Fortinet Security Processor 6 (SP6), the next generation of the custom silicon behind Fortinet's FortiGate firewalls. Intel will contribute chip design, advanced packaging, and manufacturing to the SP6 program, making Fortinet the first cybersecurity vendor named as an Intel silicon customer.

Intel told Tom's Hardware that SP6 will be built on Intel 4, the EUV process the company has so far used only for its own products, making Fortinet both the first cybersecurity vendor named as an Intel silicon customer and the first named external customer for the node. However, the announcement specifies no production timeline, and it comes in the same Q3-Q4 2026 window in which CEO Lip-Bu Tan said the company expects commitments from multiple foundry customers.

SP6 will draw on what the companies described as Intel's expertise in disaggregated semiconductor design and advanced packaging tailored for both AI-enabled and cost-sensitive applications.

That points to a chiplet-based part, which would be a departure from the current SP5, a monolithic 7nm Arm-based SoC that Fortinet launched in 2023 for its entry-level and mid-range FortiGate appliances. The deal will help Fortinet "accelerate and strengthen our ASIC strategy," said Ken Xie, founder, chairman, and CEO of Fortinet, in the announcement.

Intel 4 was the company's first process node to use EUV lithography and entered high-volume manufacturing at Fab 34 in Ireland in September 2023, where it produces the compute tile for Meteor Lake-based Core Ultra chips. The node didn't appear among the processes Intel listed for external foundry customers in its fiscal year 2024 annual report, which named 18A, Intel 3, Intel 7, Intel 16, and a 12nm process co-developed with UMC. Intel said the SP6 work reflects plans it laid out for Intel 4 several years ago, including support for custom networking ASIC workloads.

Microsoft agreed in early 2024 to build an unnamed custom chip on Intel's 1.8nm-class 18A node, a deal that reportedly covers a next-generation Maia AI processor. That announcement followed a similar pattern, with no product details, node variant, or timeline at signing and specifics emerging over the following 18 months.

Intel CFO David Zinsner said in March that the company was fielding inbound interest in 18A-P from prospective foundry customers as yields improved, and Tan told CNBC in May that foundry commitments were expected in the second half of 2026.

Fortinet does bring real volume, though, if not marquee volume. IDC ranked Fortinet first in firewall appliances shipped as of early 2023, with a 48% unit share. The company ships its own ASICs across its entry-level and high-end FortiGate ranges, and SP6 extends a silicon program now in its sixth generation.

Neither company committed to work beyond SP6, though the release described the agreement as a starting point, with further collaboration on chip technology and manufacturing under discussion.

Intel just announced another round of layoffs more than a year after CEO Lip-Bu Tan warned of “tough decisions” required to get the company back on track. This decision has resulted in the reduction of its headcount by more than 35,000 since 2024, when ex-CEO Pat Gelsinger revealed that its data center and foundry divisions have lost $1.6 billion. The latest announcement came months after the last job cuts and is still happening despite the company posting a strong first quarter this year. According to Oregon Live, its share price has more than tripled from a low of $23 per share to more than $96 today, with the data center group reporting sales of $5.1 billion for the first quarter. However, this good performance seems not to have affected the firm’s plan to streamline its operations.

“As part of our broader strategy to become a more focused and efficient company, (the data center group) is aligning its organization to ensure it has the right roles and skills in place to position the business for long-term success,” Intel told the publication in a statement. It also added, “We are committed to treating all impacted employees with respect and providing resources to support them through this transition.” Unfortunately, the company did not say how many positions will be cut and when it is happening — it only assured that the reduction-in-force won’t affect its business commitments and plans to launch new products.

While the AI infrastructure build-out was initially powered by GPUs and memory chips, advancements in agentic AI have greatly increased the demand for CPUs, putting Intel in a good position with its Xeon chips. Aside from that, the company is reporting customer interest, possibly including Apple, for its 18A and 14A nodes. It’s also planning to launch an AI GPU in the latter half of 2026 that will compete against Nvidia’s RTX Pro 5000 GPU.

This is a slow reversal of its misfortunes in the first half of the decade, but it seems that it’s not happening fast enough for its data center group employees who will be affected by the job cuts. It’s quite surprising that Intel plans to gut its Data Center group, which is one of its strongest performers and is in a good position to take advantage of the ongoing AI data center boom. But despite the high demand for AI data centers, it seems that the company still needs to cut its personnel count to streamline its operation.

Intel was expected to unveil its next-generation desktop processors later this year. The upcoming Nova Lake lineup has been making the rounds online, and a new report from VideoCardz suggests that Intel could introduce it under the Core Ultra Series 400 branding. For context, the current Arrow Lake and Arrow Lake Refresh desktop CPUs follow the Core Ultra Series 200 naming scheme, while Intel's latest Panther Lake mobile processors carry the Core Ultra Series 300 branding.

The report also claims to reveal the review embargo windows and launch timeline for several Nova Lake models. According to the report, Intel will initially introduce a 28-core DS package, which is expected to launch between January and March 2027. The new DS suffix is said to be an internal package designation for processors featuring dual-compute tiles. This will reportedly be followed by 28-core K-series (unlocked) models between March and April 2027, while 16-core and 8-core variants are expected to arrive between late March and May 2027. The flagship 52-core DS model is reportedly scheduled for a much later launch, potentially between late May and September 2027.

While Intel is yet to officially confirm a launch date for Nova Lake, various leaks have suggested that the lineup could be one of the company's biggest generational leaps in recent years. The flagship desktop SKU, featuring a 52-core configuration, is expected to combine 16 Coyote Cove Performance (P) cores, 32 Arctic Wolf Efficiency (E) cores, and four Low Power Efficiency (LPE) cores. This would be a notable jump over the current Core Ultra 9 285K, which features a total of 24-cores. The introduction of Coyote Cove and Arctic Wolf also points to an entirely new CPU architecture, replacing the Lion Cove and Skymont cores found in Arrow Lake.

Nova Lake is also rumored to bring new platform upgrades including support for DDR5-8000 memory, up to 24 PCIe 5.0 lanes for expansion, Thunderbolt 5, and Intel's next-generation Xe3 Celestial integrated graphics. The processors are also expected to feature an upgraded NPU5 for AI workloads along with a 150W Processor Base Power (PBP) and 253W Maximum Turbo Power (MTP) on the flagship model, despite the substantial increase in core count. Earlier reports have also indicated that Nova Lake will transition to a new LGA1954 socket, meaning users will likely need a new motherboard to upgrade from the existing Arrow Lake platform.

Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Intel announced a €5 billion ($5.7 billion) investment on Monday to expand chip production at its Leixlip campus in County Kildare, Ireland, upgrading existing fabs to increase output of Intel 3 wafers for Xeon 6 and next-gen server processors. The program accounts for roughly 30% of Intel's planned 2026 capital expenditure of about $17 billion, adds several hundred permanent roles to a 4,900-strong Irish workforce, and is scheduled to be substantially deployed by the end of 2027. Naga Chandrasekaran, Intel's chief technology and operations officer and general manager of Intel Foundry, told Reuters that "the demand for servers, the demand for AI is driving a significant increase in the need for Intel 3 wafers."

The announcement comes just shy of a year after CEO Lip-Bu Tan cancelled Intel's planned €30 billion fab complex in Magdeburg, Germany, and a €4.6 billion assembly and test plant in Wrocław, Poland. Those cancellations came with a memo in which Tan wrote that Intel had "invested too much, too soon – without adequate demand."

The Ireland program, however, passes the test Magdeburg failed on every measure that Intel boss Lip-bu Tan set: It uses cleanrooms that already exist; it's funded from Intel's own capex with no announced state aid; and it expands an already shipping revenue product into a demand pipeline Intel says currently exceeds its supply.

What €5 billion buys

It’s understood that no new manufacturing plants are part of the program, with the money instead going to upgrades of existing fab facilities, installation of leading-edge production equipment, and an expansion of the automated track system that links the campus's manufacturing modules into a single production flow. Intel said the work began earlier this year and will employ around 2,000 specialized tradespeople during the build-out, on top of the permanent hires.

Fab 34 is the focal point of the spending, with Chandrasekaran telling the Irish Times that "Ireland is our centre of excellence for Intel 3; we are not running Intel 3 in any other Intel manufacturing facilities." The fab began high-volume production on Intel 4 in September 2023, as the first EUV facility in Europe, and it now runs both Intel 4 and Intel 3, producing compute tiles for Core Ultra parts and Xeon 6 server processors. Intel has spent more than €30 billion in Ireland since 1989, over half of it between 2019 and 2023, doubling the campus's manufacturing footprint.

The spending follows directly from a transaction Intel closed in April, when it bought back the 49% stake in the Fab 34 joint venture it had sold to Apollo-managed funds for $11.2 billion in 2024, paying $14.2 billion to reclaim it. Apollo walked away with a roughly 27% gain in under two years. Intel now owns 100% of every wafer Leixlip produces, so each additional Intel 3 wafer the €5 billion generates flows entirely to Intel's own margin, rather than being shared with an outside capital partner.

The projects Intel cancelled

Magdeburg had roughly €9.9 billion in pledged German subsidies attached when Tan killed it, and Wroclaw had €1.9 billion in approved EU state aid. Fab 38 in Kiryat Gat, Israel, remains paused, and the Ohio site has slipped to around 2030. Every leading-edge wafer Intel produces for the foreseeable future comes from three U.S. states and one Irish campus, a concentration that made Leixlip the only European site left to expand and the cheapest place anywhere in Intel's network to add advanced capacity quickly, since the shells, EUV tools, and workforce are already in place.

Intel's Data Center and AI revenue rose 22% year over year to $5.1 billion in Q1 2026, and CFO David Zinsner told analysts on the April earnings call that Intel faces "unprecedented demand for silicon," with demand exceeding supply across the company's server lines. Intel Foundry revenue grew 16% to $5.4 billion in the same quarter, but external foundry revenue was just $174 million against a $2.4 billion operating loss, so the wafers that pay for Leixlip's tools are overwhelmingly Intel's own Xeon chips, rather than customer designs. A single campus running the entirety of a revenue-critical node also concentrates risk: Any disruption at Leixlip has no second source, because Intel 3 exists nowhere else.

Europe's most advanced node, without European money

Intel 3 is now the most advanced process technology manufactured anywhere in Europe, and Chandrasekaran told the Irish Times the expansion provides "a technology sovereignty within the EU that the EU is targeting." Interestingly, no EU or Irish state aid accompanied the announcement, which distinguishes it from TSMC's €10 billion ESMC fab in Dresden, where the European Commission approved a €5 billion funding package for a plant producing 28/22nm and 16/12nm chips for automotive and industrial customers, scheduled to be operational from late 2027. Europe's only leading-edge logic production is self-funded by an American company for its own products, while its subsidized flagship project makes trailing-edge silicon.

Commercial electricity in Ireland runs up to twice the rates Intel pays in Arizona or Taiwan. Intel warned Irish ministers in August 2025 that its competitiveness was under threat from energy costs, and the company flagged up to 195 mandatory redundancies at Leixlip in mid-2025 as part of its global workforce reduction. IDA Ireland paid Intel €30 million in 2023 to offset elevated EU power bills, so that "self-funded" framing has at least one recent caveat.

Meanwhile, Intel's 14A node is being developed in Oregon; no Irish role in it has been announced, and two prospective 14A customers will decide the node's fate in commitments expected between late 2026 and early 2027. Ultimately, the €5 billion makes Leixlip the fully-loaded workhorse of a node Intel will eventually move past, not a contender for the leading edge. Whether Europe gets anything newer than Intel 3 remains to be seen.

Intel this week announced that it will invest €5 billion ($5.7 billion) to expand and modernize its manufacturing operations at the company's facility near Leixlip, Ireland. The project is intended to increase production capacity for Intel Xeon 6 processors and next-generation Intel Xeon products built using the Intel 3 fabrication process (3nm-class), as well as advanced research and development (R&D) activities at the site.

The upgrade of the facility will involve installation of new tools presumably at Fab 34 as well as extensive infrastructure improvements designed to increase manufacturing efficiency. One of the key elements of the project is the expansion of the campus' automated material transport network, which will connect separate manufacturing modules into a single high-speed production system. Meanwhile, the modernization will not involve cleanroom expansion. Intel expects the upgrade to enable the Leixlip site to produce larger volumes of Intel 3-based products and make better use of the existing cleanroom capacity.

Intel opened its Fab 34 near Leixlip, Ireland, in 2023 and has been making various chips — including Core Ultra 100-series using Intel 4 and Xeon 6 using Intel 3 production node — using its process technologies that rely on EUV lithography at the site. At present, Intel's Fab 34 is Europe's only high-volume semiconductor production facility that uses EUV tools.

In mid-2024, Intel announced the €10.1 billion sale of a 49% stake in Fab 34 with Apollo Global Management as it badly needed money. This April, the company announced that it would repurchase the 49% stake in Fab 34 for $14.2 billion, which opened doors to the current expansion and investment. Intel claims that it kicked off execution of the project earlier this year, though it did not disclose when the upgrades will be completed.

"By investing in our existing fabs with state-of-the-art technology and installing cutting-edge tools, we are not just increasing output of critical products like Xeon 6 and next gen Intel Xeon processors built on Intel 3, we are ensuring that Ireland remains at the forefront of the world's most advanced manufacturing ecosystems, while strengthening the region’s role in the global technology landscape," said Naga Chandrasekaran, Executive Vice President, Chief Technology and Operations Officer and General Manager of Intel Foundry.

Among other things, Intel says that the investment will strengthen Europe's semiconductor supply chain and support the European Union's technology sovereignty objectives by increasing domestic production of leading-edge CPUs. There is a catch about that claim, though. All the silicon produced in Ireland is transported back to the U.S. for testing and assembly, as well as makes the end products, such as Core Ultra or Xeon 6, 'made in America.'

Intel has unveiled Starfire, a space-grade system-on-chip designed for the U.S. government that pairs eight CPU cores and a three-tile NPU built on its Intel 18A node with an Intel 3 graphics tile, all in one Foveros package. Intel published the Starfire sell sheet, listing two versions that draw 10 W and 35 W and reach up to 45 and 75 TOPS, respectively, rated to run between -55 and 125 Celsius.

Both SKUs share the same layout of four Intel 18A P-cores, four low-power efficiency cores, a three-tile NPU also on 18A, and a four-core Xe GPU with 64 execution units built on Intel 3. The Low Power part runs its P-cores at 1.0 GHz, efficiency cores at 850 MHz, and the GPU between 800 MHz and 1.0 GHz. The Performance part clocks the P-cores to 3.1 GHz, efficiency cores to 2.1 GHz, and the GPU to 2.0 GHz. Both carry 12 PCIe Gen4 lanes, support LPDDR5 or DDR5, and are rated for a 10-plus year lifetime.

Intel builds the CPU and NPU on 18A and the GPU on the older Intel 3, the same node division it used for Clearwater Forest, the 288-core Xeon that stacks 18A compute tiles on Intel 3 base tiles. Smaller transistors hold less charge per stored bit, which makes leading-edge silicon more prone to radiation-induced bit flips, so committing 18A to orbit leans on RibbonFET and design-level hardening rather than a mature, inherently more tolerant node.

The market Starfire is targeting has run on BAE Systems' RAD750 for two decades. That radiation-hardened PowerPC part clocks 110 to 200 MHz, carries 10.4 million transistors, and is built on 150nm or 250nm lithography, per public specifications, and it flies on the Mars rovers, Kepler, and Fermi, among more than 150 spacecraft. BAE's multi-core RAD5545 and the Microchip-built processor NASA is developing to reach 100 times the throughput of current spaceflight chips are the more recent step up. Starfire's up to 75 TOPS and dedicated NPU put it in a different bracket, built for on-orbit AI inference rather than telemetry and control.

Intel lists the radiation data, covering total ionizing dose, single-event latch-up, and single-event effects, as characterization in process, so the part isn't radiation-qualified yet, and it notes the specs are subject to change. Intel Government Technologies is handling Starfire, with samples in Q3 2026 and a pitch of market-competitive pricing and domestic manufacturing. Intel Foundry is the only U.S.-based maker of leading-edge logic, holds Trusted Foundry status, and has tied its 18A and packaging roadmap to Pentagon programs including RAMP-C and SHIP, though 18A yields aren't expected to reach industry-standard levels until 2027.

Intel is working on a version of its Nova Lake-S processor platform codenamed Dunlow that will offer up to 28 cores and will target entry-level server and workstation applications, according to shipment manifests located in the NBD database by @x86deadandback.

Formally, Intel's codenamed Dunlow platform will succeed the company's Catlow platform with Xeon 6300P-series CPUs and will support Xeon E-class Nova Lake-S processors (presumably) with up to 28 cores that feature a dual-channel memory subsystem, come in an LGA1954 form-factor, and have a processor base power of 95W, according to shipments manifests at NBD data.

Intel's next-generation Core Ultra 400-series platforms for desktop computers, codenamed Nova Lake-S, allegedly feature up to 52 cores, which include up to 16 high-performance Coyote Cove cores and up to 32 energy-efficient Arctic Wolf cores in the compute tile, as well as four low-power Arctic Wolf cores presumably in the SoC tile. These Nova Lake-S CPUs are aimed at enthusiasts and reportedly pull up to 474W with a single purpose: to offer unbeatable performance and feature set to put Intel back on the map of enthusiast-grade platforms currently dominated by AMD.

By contrast, the Dunlow platform seems to be a completely different kind of animal. The CPU deliberately features 28 cores and up to 95W PBP (TDP). All Xeon processors except Xeon 6700E, Xeon 6+, and some Atom-based solutions for specialty applications released to date have only featured high-performance cores. Even Intel's Xeon 6300P-series 'Raptor Lake-E' based products feature up to 12 P-cores to offer higher sustained all-core frequencies. Therefore, unless Intel plans to offer energy-efficient cores in its next Xeon CPU aimed at entry-level servers and workstations, we may be dealing with a very special processor that features 28 P-cores that is designed to beat all desktop-grade platforms in demanding applications.

While, for now, 28 P-cores inside Nova Lake-S processors for the Dunlow platform is speculation, it should also be noted that 28 cores do not naturally derive from a 16P+32E desktop design and are impossible to derive from a notebook-grade 8P+16E design. Also, Intel typically does not create server/workstation products by fusing off nearly half a desktop die (it does not even matter whether it disables some P-cores and some E-cores, disabling 20 cores in a 48-core tile hardly makes a lot of sense).

A Nova Lake-S CPU for Dunlow featuring a compute tile with 28 P-cores would resemble the abandoned Raptor Lake-32C, which featured an all-P-core design aimed at workstations and entry servers before being canceled. It is also possible that this could be a derivative of a small Xeon die adapted to an LGA1954 packaging and dual-channel memory to reduce platform costs. At the end of the day, many server applications like storage or web hosting do not need extremely high memory bandwidth, so two DDR5 channels could be enough.

Another reason for Intel to release a Nova Lake-S CPU with up to 28 P-cores is to fill the gap between high-end enthusiast-grade desktops that feature up to 16 P-cores and expensive Xeon 6 server and workstation CPUs that may start at 16 cores, but feature an octa-channel memory subsystem that is costly and is an overkill for many applications. Also note that since Xeon 'Diamond Rapids' processors with an octa-channel memory subsystem have been canceled, the gap between desktop and high-end server CPUs just gets way too wide in 2028, making Nova Lake 28 P-core silicon a potentially viable option.

An Intel patent application published on July 2, 2026, surfaced by Underfox, has revealed the company's plans for a new high-bandwidth memory (HBM) architecture that aims to ease the packaging and cost bottleneck of today's interposer-based HBM. The patent application — filed back on December 26, 2024 — describes what Intel calls cross-batch memory (XBM), an "ultra-high-bandwidth memory with backend transistors" built with the goal of matching HBM4's footprint while swapping conventional DRAM and its ultra-wide interface for back-end-of-line (BEOL) transistors and serial Universal Chiplet Interconnect Express (UCIe) links.

Intel's proposed design is a memory stack that addresses the assembly costs that make conventional HBM expensive by dropping the costly silicon interposer and shrinking the package, while building in its own defect repair.

The filing lays out a stack of memory dies, each holding one-transistor one-capacitor (1T1C) DRAM fabricated in the back-end-of-line, wired together with through-silicon via (TSV) "gutters" and both-sided high-bandwidth interconnect (HBI) connections. Intel describes dies of roughly 1.5 gigabytes (GB) apiece — 768 "datablocks" arranged in a 32-by-24 grid, grouped into eight channels of eight sub-channels each — stacked eight high and scaling to 16. Data then leaves the stack over UCIe I/O bundles running at 32 gigatransfers per second (GT/s), funneled out through a base die.

To understand what Intel is changing, it helps to recall what standard high-bandwidth memory does. HBM stacks DRAM dies vertically on a base logic die, threads them together with TSVs, and communicates with the processor across a silicon interposer using an extremely wide parallel interface — on the order of 1,024 bits per stack. This width is how HBM delivers its bandwidth, but it is also what makes it expensive to package and hard to scale, as every one of those wires has to be routed through an interposer sitting between the memory and the compute die. As AI accelerators have outrun the rate at which memory can feed them, this "memory wall" has become the dominant constraint on performance, which is why nearly every large chipmaker is now attacking the interface and the stack rather than the logic.

XBM's first major change is structural. Conventional DRAM cells are built in the front-end-of-line, the base silicon layer where transistors are normally fabricated. XBM instead moves the 1T1C cell into the back-end-of-line, the metal-and-via stack above the transistor layer, using thin-film transistors. Building memory in the BEOL is what lets Intel pack the die into many small, independently addressable memory blocks, and it is the same backend-transistor direction Intel has pursued for placing memory directly over logic.

The second change is the interface. Rather than HBM's wide parallel PHY, XBM serializes data onto UCIe bundles at 32 GT/s, with the base die handling the serialize/deserialize step and routing all I/O to the compute die. Moving to a standard chiplet interconnect is what makes the design "chiplet-native" and, Intel argues, simpler and cheaper to package than an interposer-bound HBM stack. The tradeoff is that 32 GT/s is UCIe's current top data rate, so the interface is already running at the spec ceiling rather than leaving obvious headroom.

Intel also leans heavily on repairability. The base die carries dedicated spare channels, built-in self-repair (BISR), decode and debug logic, and four sub-channels of redundant memory arrays that act as fungible spares for defects in the dies above — post-assembly repair designed to claw back yield on a very tall stack.

A large portion of the patent application focuses not on the memory cell at all but on how to mount it. Intel details memory-on-package (MoP) and "reversed overhang" structures aimed at cutting the stack's Z-height — conventional MoP can add 300 to 350 micrometers (µm) — while removing the stiffener normally needed to control warpage and feeding DRAM power directly from the voltage regulator. This is the concrete basis for the "smaller, cheaper package" claim.

XBM should not be confused with ZAM (Z-Angle Memory), the architecture Intel is co-developing with SoftBank subsidiary SAIMEMORY and set to present at the VLSI Symposium 2026. ZAM's innovation is on the bonding side — a fusion-bonded, nine-layer stack of largely conventional DRAM with roughly 3-µm-thin silicon between tiers — and it reportedly targets around twice HBM4's bandwidth density, with commercialization aimed at 2029. XBM, by contrast, is an Intel-only filing that changes the DRAM transistor itself and the interface. Read together, they suggest Intel is running at least two parallel HBM alternatives, a fitting move for a company that began in 1968 as a memory maker.

The caveats on Intel’s proposed HBM architecture are the usual ones for a patent. The patent was filed 18 months ago, and there’s currently no product or roadmap, signaling potential intent rather than a shipping part. The UCIe interface is already at its rate ceiling, backend-transistor DRAM remains unproven at manufacturing scale, and the whole thing still has to justify itself against HBM4E and Intel's own ZAM timeline.

Nvidia shouted proudly in a recent blog post that its network of American manufacturing partners and suppliers now spans 43 states, that TSMC's Phoenix plant is producing Blackwell wafers at volume, and that it plans to produce up to $500 billion of AI infrastructure in the U.S. over four years with partners including TSMC, Foxconn, Wistron, Corning, Coherent, and Amkor. Intel has made its own case in an America 250 post presenting end-to-end U.S. capabilities across design, manufacturing, and advanced packaging.

Both accounts hold up at the wafer stage but omit the same downstream step: every Blackwell die that leaves TSMC's Arizona fab still crosses the Pacific to be packaged, no HBM is manufactured or packaged on U.S. soil, and the facilities intended to close those gaps won’t start production until 2028 at the earliest.

Lofty projects

Foxconn is building a Houston factory to produce GB300 tray modules for Nvidia, and Wistron will assemble and test Nvidia AI systems at a new facility in Fort Worth, Texas. Coherent broke ground in June on an expanded Sherman, Texas, plant that the company describes as the first volume-production 6-inch indium phosphide fab, supplying the lasers and optical components that link AI systems together.

Corning is adding more than 3,000 jobs across optical manufacturing sites in North Carolina and Texas. The post also cites an estimate from consultancy Public First that Nvidia-driven AI demand will contribute $485 billion to U.S. GDP in 2026 and support over 100,000 jobs. “AI is driving a once-in-a-generation opportunity to reinvigorate American manufacturing and supply chains,” said Nvidia’s Jensen Huang in the post.

Meanwhile, Intel's post lists R&D and manufacturing across Oregon, Arizona, New Mexico, and California, describes Ohio as “a planned site,” and devotes most of its length to workforce programs, K-12 AI education, and the company’s America250 partnership. Neither post addresses where the most advanced AI processors are actually assembled into finished chips.

The Pacific round-trip

Nvidia and TSMC produced the first Blackwell wafer at Fab 21 near Phoenix last October, and the site has since moved to volume output of Blackwell silicon on TSMC's 4NP node, the custom 4nm-class process built for Nvidia. On the other side of the Phoenix metro area, Intel's Fab 52 became fully operational in the same month as the first high-volume home of Intel 18A, and Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is capable of more than 10,000 18A wafer starts per week. Panther Lake reached broad availability in January, Clearwater Forest is due in the first half of this year, and 18A yields are expected to reach industry-standard levels in early 2027, which I covered in my examination of Intel's fab roadmap.

This ultimately means that leading-edge logic wafers are now being fabbed in the U.S. by two companies on two competing nodes. That’s a genuine change and, by any measure, a monolithic achievement when compared to the start of the decade, and neither company overstates that in their corporate blogs.

However, a Blackwell data center GPU pairs two reticle-sized compute dies with eight stacks of HBM3e on a silicon interposer using TSMC's CoWoS-L packaging, and all of TSMC's CoWoS capacity is located in Taiwan. TSMC’s U.S. facilities currently send 100% of their chips to Taiwan for packaging, including wafers fabbed in Phoenix. A Blackwell die fabbed in Arizona therefore travels roughly 7,000 miles to be diced, stacked, and mounted, then travels onward through system assembly before any of it returns to a U.S. data center.

As for HBM, every stack in production today comes out of SK hynix and Samsung facilities in South Korea or Micron's fabs in Taiwan and Japan, and the ABF substrates beneath the interposer are similarly concentrated in Japan and Taiwan. No U.S. facility currently manufactures or packages HBM. The one company running advanced packaging at scale on U.S. soil is Intel, whose Foveros operation in New Mexico handles its own 3D-stacked products and has started attracting outside interest; Google has reportedly booked Intel to package more than 3 million TPUs in 2028. Intel doesn’t currently appear anywhere in Nvidia's list of manufacturing partners.

Nothing before 2029

Amkor also broke ground on its Peoria, Arizona campus last October, a $7 billion, two-phase project with up to 750,000 square feet of cleanroom, roughly $400 million in CHIPS Act funding, and Apple and Nvidia signed as lead customers. Its first factory will be completed in mid-2027, with production beginning in early 2028. TSMC formalized the relationship on June 16th, signing a 10-year agreement under which it will procure packaging and test services from Amkor, while TSMC executives said in April that the foundry's own Arizona packaging facility will bring CoWoS and 3D-IC capacity online before 2029.

SK hynix began initial work in April on its $3.87 billion advanced packaging plant in West Lafayette, Indiana, targeting mass production of HBM4E and HBM5 in the second half of 2028, the same window Amkor’s aiming for. The timing means the entire Blackwell family, and likely the first Rubin generation, will complete their product lifecycles without a fully domestic manufacturing path. The first AI accelerators that can be fabbed, packaged, and fitted with U.S.-packaged memory without leaving the country will be HBM4E-era parts arriving around 2028 to 2029.

Unfortunately, the Section 48D advanced manufacturing tax credit, raised to 35% last July, doesn’t apply to projects whose construction begins after December 31st, 2026, which gives Coherent's June groundbreaking, SK hynix's April piling work, and Amkor's October start a shared fiscal deadline if they want to benefit from it.

As for Foxconn and Wistron’s Houston and Fort Worth plants, they’ll receive GPUs packaged in Taiwan and assemble them into trays, racks, and systems on U.S. soil. It’s that type of assembly work that’s carrying most of the $500 billion figure, which counts the value of AI infrastructure produced rather than capital spent on factories. Wafers are American, racks are American, but everything in between isn’t. Whether that changes on schedule is a question for 2028, and it depends highly on two packaging campuses in Arizona and one in Indiana meeting their deadlines.

Intel on Friday confirmed that it had increased prices of some of its consumer and server CPUs, citing market dynamics, rising costs, and soaring demand for these products. While select enthusiast processors increased from $30 to $50, data center-grade products increased by hundreds, if not thousands, of dollars. Intel is among many suppliers that have recently hiked prices of their products, citing increasing costs and demand that exceeds their supply.

"The recent pricing updates reflect current market dynamics, including rising supply chain costs and strong demand for our Intel Core Ultra 200S Plus processors," an Intel spokesperson told Tom's Hardware. "These updates are in line with recent price increases for other Intel product families based on similar factors."

This week it turned out that Intel had quietly increased recommended customer prices (RCPs) of its latest Core Ultra 200-series Plus processors for desktops — the Core Ultra 7 270K Plus and the Core Ultra 7 250K Plus — by $30 - $50, depending on the model. Both processors belong to the Arrow Lake family and, like the rest of them, are produced by TSMC. Yet, Intel's original 'non-Plus' Core Ultra 200-series processors did not increase their MSRP. The flagship Core Ultra 9 285K still carries a $599 RCP, just like it did at its launch in Q2 2024. Something similar applies to the least advanced Arrow Lake processor for desktops — the Core Ultra 5 225 — that has an RCP between $183 and $236, which is a bit lower than its launch RCP of $241.

If Intel did see supply-chain inflation, it would be reasonable to expect the company to adjust prices of the whole family. Instead, the company raised prices only on select products that apparently had become unexpectedly attractive to customers who can afford them and who have probably demonstrated willingness to buy them above recommended prices. This means that we are not dealing with a simple cost pass-through, but rather with a price hike associated with strong demand for specific SKUs.

When it comes to data center-oriented processors, we see rather massive price hikes. While higher-end Xeon 6 'Granite Rapids' CPUs cost less than they used to at launch in 2024, they are noticeably more expensive after Intel slashed their recommended prices in 2025, and they can be twofold higher when compared to retail prices from mid-2025. Perhaps the biggest surprise is that select Xeon 8000-series 'Emerald Rapids' processors now carry higher RCPs than they used to when they were released in late 2023.

All Intel Xeon processors are produced internally (so Intel cannot blame higher costs on TSMC), and while Intel gets raw materials from its partners, it is doubtful that overpriced photoresist can significantly affect RCPs of CPUs that sell for thousands of dollars. Meanwhile, Intel has been saying for several quarters now that demand for its Xeon processors exceeds supply. Therefore, it makes a lot of sense for Intel to finally capitalize on that and increase RCPs of popular models.

There is a caveat, though. Actual prices of data center hardware tend to differ from list prices as they depend on many factors, including volumes and strategic relations between suppliers and consumers. To that end, while it is evident that Intel has increased RCPs of its Xeon CPUs, it remains to be seen how this affects its average selling prices (ASPs) for the ongoing quarter and for the whole year.

Intel has resolved wafer-to-wafer yield variability issues with its 18A process technology, according to a report from BlueFin Research Partners. If the report coming from an unofficial source is accurate, then Intel can expect consistent and predictable yield improvements for its products made using the latest 1.8nm-class node from now on.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

Intel released its new Core Ultra 200S Plus desktop processors back in March 2026, and it appears that the company has quietly increased their prices. According to Intel's official product page, the Core Ultra 270K Plus now has a recommended customer price of $339–$349, up from the previous $289–$299. Similarly, the Core Ultra 250K Plus has increased from $189–$199 to $219–$229.

While the increase amounts to an additional $30–$50 (depending on the model), it is worth noting that these higher prices have already been reflected on Amazon. We have reached out to Intel to confirm the pricing changes and will update this article if and when the company responds.

The Core Ultra 270K Plus and the 250K Plus are part of Intel’s Arrow Lake Refresh lineup and were introduced with a relatively low price compared to their non-Plus predecessors. Intel claimed up to 15% improvement in gaming performance at 1080p compared to stock Arrow Lake chips thanks to several key improvements aimed at addressing the architectural bottlenecks of the original Arrow Lake processors.

The Core Ultra 7 270K Plus comes with 24 cores, including 8 P-cores and 16 E-cores, which is similar to the more expensive Core Ultra 9 285K. The Core Ultra 5 250K Plus comes with 18 cores across 6 P-cores and 12 E-cores, which is slightly below the 20 cores available on the Core Ultra 7 265K. Intel also increased the die-to-die interconnect frequency by 900 MHz to reduce latency and improve gaming performance.

The new chips also offer native support for faster DDR5-7200 memory, as opposed to 6400 MT/s on the non-Plus Arrow Lake chips. Then there’s Intel's new Binary Optimization Tool, a free software utility that analyzes executables and automatically recompiles them with CPU-specific optimizations. According to Intel, this alone is responsible for a significant portion of the gaming performance gains.

While the increase in price may hamper the value advantage that these chips initially offered, there is no doubt that they bring meaningful performance to the table. In our testing, we found the Core Ultra 7 270K Plus to deliver excellent productivity performance with a noticeable uplift in gaming over the original Arrow Lake chips. In fact, it is currently the best Intel CPU on the market. As for the Core Ultra 5 250K Plus, it offers one of the strongest value propositions at its price point. It also remains our top pick for the best budget CPU, thanks to its ability to compete with similarly priced gaming processors while excelling in heavily threaded workloads.

Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

Tesla has hired Gary Jiang, an Intel veteran who most recently was responsible for installing equipment and transferring Intel's leading-edge 18A technology process from development fab in Oregon to the company's high-volume fab in Arizona, as spotted by Electrek.co. The appointment marks the first publicly identified senior leadership hire for Elon Musk's semiconductor production project, Terafab, which demonstrates Tesla's effort to build an experienced semiconductor manufacturing organization from the ground up by hiring veterans from other companies.

Tesla poaches an Intel veteran

Gary Jiang joined Tesla in June 2026 after spending over 17 years at Intel, according to his LinkedIn profile. Interestingly, there is little to glean about his current role from his LinkedIn profile, aside from noting that he is a director at Tesla. His final position at Intel was as Factory Manager, where he oversaw the construction of the production facility, the installation of fabrication equipment, factory startup, product certification, preparation for high-volume manufacturing, and, ultimately, the transfer of Intel 18A technology from the development fab in Oregon to high-volume Fab 52 in Arizona.

Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies (which include Intel 10nm SuperFin and 10nm Enhanced SuperFin/ Intel 7) at Fab 32 and Fab 42.

Tesla has been looking for a Technical Program Manager (TPM) for semiconductor infrastructure, focused on end-to-end fab program delivery, since March, but without any success, as the job listing is still listed on the company's website. Therefore, Terafab — the joint initiative between Tesla, SpaceX, and xAI — still does not have a formal leader who is going to lead the whole project.

In his most recent role at Intel, Gary Jiang worked closely with supply chain, finance, and materials logistics for new factory planning for output, wafer cost, yield, and profit & loss, according to his LinkedIn profile. He also managed the billion-dollar capital equipment and startup of the fab. Hence, without any doubt, Jiang appears to have been one of the senior manufacturing leaders responsible for building and equipping Intel's new 18A-capable manufacturing facilities in Arizona (primarily Fab 52, and potentially Fab 62 as the campus expands). However, it would still be inaccurate to say he was the person responsible for building Fab 52 alone.

Jiang's skills roughly match what one would expect from a senior manufacturing executive helping commission a new leading-edge fab, so he will be instrumental in turning a newly constructed fab shell (or even cleanroom) into a production-ready semiconductor manufacturing facility.

However, he did not oversee the entire Fab 52/Fab 62 program and was not responsible for every stage of the project — from permitting and groundbreaking to construction, tool installation, and the ramp to high-volume manufacturing. Likewise, he is unlikely to lead the Terafab project as a whole. Nonetheless, given that Terafab is set to license Intel's 14A process technology, Gary Jiang is probably among the best candidates to equip a fab for an Intel manufacturing node.

One major caveat

In fact, one of the most confusing parts about Tesla's hiring people to work at Terafab is that Tesla itself will not own any high-volume semiconductor production facilities; SpaceX will, according to Elon Musk.

In the near term, Tesla plans to build a $3 billion semiconductor R&D center at its Texas campus. The facility will house a small pilot line capable of processing a few thousand wafers per month to develop and validate new manufacturing technologies before they are scaled for commercial production.

Once the pilot line shows signs of success, SpaceX is expected to construct a full-scale high-volume manufacturing fab. However, coordinating a joint project between Tesla and SpaceX will add complexity, as major decisions require approval from both companies' boards and must undergo conflict-of-interest reviews, which will likely slow execution.

That said, given that Gary Jiang was hired by Tesla, not SpaceX, his responsibilities could be to equip and ramp a development facility at its Gigafactory Texas campus rather than build, equip, and ramp a high-volume fab for SpaceX. In any case, we are speculating here, and nothing can really stop SpaceX from hiring Jiang at some point down the line.

Leading Japanese capsule toy maker Tarlin International has announced an official collaboration with “the four major manufacturers” of the PC components industry. The teased result means that gachapon fans will be able to get their hands on tiny models of ASRock, Gigabyte, MSI, and Intel parts (plus fans, PSUs, and cases), accurate enough “that you can assemble and play with.” In 2026, PC building has become so expensive that perhaps Tarlin’s latest wares will fill an emotional vacuum in the market.

In the image above, you can see Tarlin has inked some kind of official licensing deal with ASRock, Gigabyte, MSI, and Intel. There’s already been four series of networking equipment gachapon launched by Tarlin, for some context.

As far as we can see from the social media posting, the new Tarlin gachapon series includes three branded miniature motherboards: the ASRock Z890 Steel Legend WiFi, the Gigabyte Z890 Aorus Elite WiFi7 Plus, and the MSI MEG Z890 Ace. Premium stuff. Intel’s Core Ultra 7 270K Plus seems to be the only CPU choice. There are also case fans, a PSU, and a tower case for your minuscule components PC build.

Tarlin’s eccentric gachapon pedigree

Compared with gachapon rivals like Bandai and Takara Tomy, Tarlin has carved a niche, eccentric furrow in the industry. It has a reputation for turning everyday, mundane, or highly technical objects into accurate scale miniatures.

Examples of other incredibly niche Tarlin-produced capsules include its Temporary Toilet Series, a realistic Articulated Crayfish, and its series of Cisco rackmount network gear toys. In this context, it's “serious spec” PC component capsule toys, which are made to such exacting precision that they can be assembled to make tiny tower PCs, aren’t so unusual.

In 2024, we spotted a Japanese capsule toy machine filled with Intel CPUs. One gacha chancer acquired an Intel Core i7-8700 CPU after inserting 500 Yen (around $3.25) and twisting the customary knob.

Intel is expected to push the boundaries on power draw with its upcoming Nova Lake series processors, which will rival the best CPUs. According to newly leaked information, the flagship 52-core desktop variant is expected to feature a dual-compute tile architecture with a massive PL2 limit of 474W. The information was shared by LC Tech Leaks and confirmed by Jaykihn, who has a pretty solid track record with Intel hardware.

PL2, or Power Limit 2, represents the maximum power a CPU can draw during short boost periods. That said, a PL2 target of 474W remains quite demanding, although a previous rumor suggests Intel may also have a PL4 emergency power limit over 700W. It is important to note that these power limits may only apply to the top-end models with the dual-tile architecture.

Additionally, the leak also sheds light on the upcoming platform, including the previously rumored LGA1954 socket. We already know that Nova Lake-S will require a new generation of motherboards. Motherboard vendors are expected to classify their boards by sustained PL1 power levels, with configurations for 35W, 65W, 125W, and 175W CPUs. Enthusiast-grade motherboards, likely the Z990 series, are also rumored to feature three EPS 8-pin CPU power connectors instead of the traditional two. While vendors will have the option to include a third connector, its primary purpose would be to support extreme overclocking and would not affect the CPU's rated performance profile.

The upcoming Nova Lake-S lineup is expected to carry the ‘Core Ultra 400S’ moniker and will be Intel's biggest desktop CPU overhaul in years. We’ve previously reported leaked specifications indicating configurations ranging from 6 to 52 cores, with support for DDR5-8000 memory. The flagship 52-core model is expected to feature 16 performance cores, 32 efficiency cores, and a new Big Last Level Cache (bLLC) design to take on AMD's 3D V-Cache gaming dominance. The company is also rumored to introduce integrated Xe3 graphics, Thunderbolt 5, PCIe 5.0 connectivity, and an upgraded NPU for AI workloads.

While these specifications are unconfirmed, it is clear that Intel is targeting substantial gains in gaming, multi-threaded performance, and overall platform capabilities with its next-gen processors.

Solidigm is arguably one of the most mysterious storage companies in the industry today. The company is a wholly owned subsidiary of SK hynix, yet unlike its parent company, which produces charge-trap flash memory, it uses floating-gate 3D NAND memory that it develops and manufactures internally at a dedicated fab in Dalian, China.

Solidigm originates from Intel's Non-Volatile Memory Solutions Group (NSG), the company's NAND and SSD business unit, which used to have a unique technology strategy that differed from that of other flash and drive producers. To that end, it is not surprising that Solidigm also has a unique positioning as it only offers data center drives, most of which are based on floating-gate memory and proprietary in-house designed controllers. Furthermore, Solidigm is a fully vertically integrated company.

At Computex 2026, we sat down with Avi Shetty, who is vice president of AI ecosystem, Solutions & Market Enablement at Solidigm. Before his current position at Solidigm, he spent 14.5 years at Intel's storage division, so he has deep knowledge both about technology and the market. During our conversation, we discussed how Solidigm keeps evolving, including floating-gate NAND memory, advanced packaging technologies, next-generation SSDs, liquid-cooled SSDs, and more.

Anton Shilov: Could you introduce yourself to our readers and describe what do you do at Solidigm?

Avi Shetty: My name is Avi Shetty. I work at Solidigm, where I help lead AI solutions and ecosystem initiatives. My team works with global platform providers, software ISVs, and ODMs to ensure Solidigm solutions are validated, benchmarked, and included in reference designs at both the device and cluster levels, enabling customers to fully utilize our products.

A part of SK hynix that acts independently

Anton Shilov: You were previously a part of Intel. How is the integration going? Are you now fully integrated part of SK hynix, or do you operate independently?

Avi Shetty: Let me provide some background. While Solidigm was established in December 2021, our history goes back decades. Many of us came from Intel's Non-Volatile Memory Solutions Group (NSG), which developed Intel’s NAND SSDs for both client and data center markets.

In 2021, SK hynix acquired Intel’s NAND and SSD business and established Solidigm. Since December 2021, we have operated as a wholly owned U.S. subsidiary of SK hynix, headquartered in Rancho Cordova, California.

Anton Shilov: So, you are part of SK hynix, but still maintain a degree of independence?

Avi Shetty: Absolutely. We operate as an independent subsidiary of SK hynix. Our strategy is focused entirely on enterprise SSDs. Every bit of [floating gate] NAND [at our fab in Dalian, China] we produce goes into enterprise storage solutions.

This is one of the ways we differentiate ourselves from competitors such as Samsung and Micron, which also serve mobile and client markets. We made a deliberate decision to focus exclusively on enterprise storage and AI.

We are also fully vertically integrated. We manufacture our own NAND, develop our own controllers, write our own firmware, and design our own SSDs. While we work with manufacturing partners to build products, we control the entire technology stack.

I also believe we are the only company with access to two different NAND architectures. Through SK hynix we have access to charge trap flash (CTF) technology, and we continue to develop floating gate NAND technology for our high-density QLC SSD products.

Anton Shilov: What is Solidigm's current share of the enterprise SSD market?

Avi Shetty: Approximately 24%. That is enterprise SSDs only. We do not participate in any other NAND markets. As of the first quarter of 2025, plus or minus a few percentage points, our measured enterprise SSD market share is approximately 24%. We evaluate market-share data quarterly and semiannually, and that is the latest figure we’ve publicly discussed.

Anton Shilov: How much of your business today is concentrated in high-capacity SSDs versus higher-performance products?

Avi Shetty: High-density SSDs now represent a significant portion of our business. Because Solidigm is privately held, we do not publicly disclose that breakdown. We report our financial metrics through our parent company, SK hynix.

What I can tell you is that both our 61TB-class and 122TB-class products became customer favorites almost immediately after launch. Demand for high-density storage has been extremely strong.

Anton Shilov: I assume you also work directly with hyperscalers?

Avi Shetty: We work with a broad range of customers globally. That includes U.S. cloud service providers, Chinese cloud service providers, OEMs around the world, NeoCloud providers, software ISVs, and channel partners. We maintain customer support, engineering, and sales organizations globally. Our business spans the Americas, EMEA, China, and the rest of Asia-Pacific.

Anton Shilov: Which customer segment represents the largest opportunity for growth right now? Traditional cloud providers or something else?

Avi Shetty: We intentionally maintain a diversified customer base.

What is interesting is how quickly new segments emerge. For example, the NeoCloud market has existed for some time, but AI-focused infrastructure providers such as CoreWeave, Lambda, Crusoe, and Nebius have become much more important over the last two years.

Before the AI boom, these companies represented only a small portion of demand. Today, they are becoming a meaningful part of the market.

As AI infrastructure continues to expand, Solidigm is adapting both its customer strategy and product portfolio to support these emerging deployments while continuing to serve our traditional customers.

Floating gate NAND in 2026

CTF NAND used by major memory makers has approached 276 - 286 active layers, whereas Solidigm's floating gate flash is still at 192 layers, meaning that the company is somewhat behind some of its rivals in terms of active layers as of mid-2026. It is set to catch up with its next generation that will have over 200 layers, but only in the second half of this year. However, floating gate NAND memory still has a number of advantages over CTF, particularly for applications that Solidigm targets.

Floating gate uses a conductive polysilicon island to store charge, which provides excellent cell isolation — charge stays well-contained and is less likely to spread to or interfere with neighboring cells — and this is particularly important for 3D QLC NAND with very high layer counts. In addition, Solidigm claims that floating gate gives a strong voltage threshold window and better cell isolation, which enables the company to keep scaling QLC more while maintaining good reliability.

Anton Shilov: Are you still producing floating gate NAND, and do you intend to continue?

Avi Shetty: Absolutely. We introduced our first QLC foating gate NAND product in 2018, and today we are on our fourth generation of QLC NAND.

Our flagship high-capacity product currently ships with 192-layer floating gate NAND technology and powers our 122TB SSD.

Anton Shilov: Haven't you also announced a larger drive?

Avi Shetty: We have announced a higher-capacity product and expect it to become available later this year.

Anton Shilov: The 256TB-class drive?

Avi Shetty: Correct. Approximately 245TB usable capacity.

Anton Shilov: So you are going to have a roughly 245TB SSD available this year?

Avi Shetty: Correct.

Anton Shilov: What advantages does Floating-Gate NAND provide?

Avi Shetty: Floating gate NAND gives us scalability. We have consistently been first in the industry to push storage density in standard form factors. We were the first to introduce a 30TB SSD, then a 60TB SSD, and later a 122TB SSD.

We have been shipping the 122TB drive for nearly five quarters. We launched it in the fourth quarter of 2024, and it has since become our flagship product. It is probably our most popular product of 2025.

The reason customers like the 122TB drive is efficiency. When you look at AI data centers, customers want low power consumption, scalability, and performance. While this particular product is a PCIe Gen4 solution, our roadmap continues to increase both density and bandwidth. You will see future products based on PCIe Gen5 and PCIe Gen6.

The real attraction of the 122TB SSD is scale. In a 1U server, you can install 24 of these drives and get nearly 3PB of storage in a single rack unit.

If you look at the AI data pipeline — from training to archiving — the first and last stages require massive datasets. That is where these high-capacity SSDs are being deployed today.

Now we are also seeing growing demand from inference deployments. Inference can run in core data centers or in edge and back-office environments. Those deployments require storage that can efficiently feed GPUs and support workloads such as context storage and KV cache management. High-density SSDs help provide the capacity required for those applications.

Next-generation SSDs: PCIe Gen6 drives with liquid cooling

Anton Shilov: You mentioned PCIe Gen5 and Gen6 [next-generation drives]. I assume you are referring both to next PCIe generations and future NAND generations?

Avi Shetty: Both.

We maintain separate technology and product roadmaps. Earlier, I mentioned that our current QLC NAND is our 4^th Generation technology based on 192 layers. We will continue investing in future NAND generations as well.

On the product side, we are talking about PCIe generations. We currently ship both PCIe Gen4 and PCIe Gen5 SSDs. All of our TLC products are PCIe Gen5 today, while our QLC lineup currently remains PCIe Gen4.

Future QLC products will move to PCIe Gen5, and eventually, we will introduce PCIe Gen6 SSDs as platform vendors such as AMD, Intel, and Nvidia adopt PCIe Gen6 in their systems.

Anton Shilov: You mentioned PCIe Gen6 SSDs. You have not shipped one yet, correct?

Avi Shetty: Correct. PCIe Gen6 products are part of our future roadmap.

Anton Shilov: How close are they?

Avi Shetty: We are not making product announcements at Computex, but you will hear more from us soon.

Anton Shilov: At the moment there is really only one platform that can take advantage of them anyway. Well, two, if you consider Nvidia Vera.

Avi Shetty: That is part of the equation. When we evaluate our roadmap, we consider demand, platform readiness, and overall value to customers.

For example, we have what we call a refresh philosophy. We may introduce a PCIe Gen4 refresh or a PCIe Gen5 refresh that lowers cost or improves efficiency rather than immediately moving to a new PCIe generation.

The question is whether customers gain more value from Gen6 today or from a more mature, lower-cost Gen5 product. Those are the kinds of decisions our planning teams evaluate.

What I can say is that Solidigm maintains a full roadmap covering PCIe Gen4, Gen5, and future Gen6 SSDs across all major form factors, including U.2, E1.S, E3.S, and other EDSFF variants. Our portfolio spans capacities from 2TB all the way to 122TB.

Anton Shilov: Launching an all-new product early still gives you time to validate products with platform vendors.

Avi Shetty: Absolutely. We already work closely with platform providers to validate prototypes long before products are launched. Our engineering teams participate in interoperability events and PCI-SIG workshops to ensure products are ready when platforms become available.

Anton Shilov: That is actually interesting because PCIe Gen6 interoperability workshops have been delayed multiple times. Back in 2024, people expected the ecosystem to move much faster and interoperability workshops to start in 2024, with the list of compatible products emerging in 2025.

Avi Shetty: That is true. A lot depends on platform readiness and ecosystem scaling. PCIe Gen6 by itself is not enough. This is my personal opinion, but to fully benefit from Gen6 storage performance, the industry must also address cooling. That is one reason we invested heavily in liquid-cooled storage.

Last year, we introduced what we believe was the world's first liquid-cooled storage solution for Nvidia environments. It used E1.S PCIe Gen5 SSDs with direct liquid cooling. Historically, liquid cooling was focused on CPUs and GPUs. We extended it to storage by allowing coolant to flow through a cold plate attached to the SSD. The cold plate removes heat directly from the drive. To fully exploit PCIe Gen6 performance, the ecosystem must develop those kinds of technologies as well.

Anton Shilov: So you believe PCIe Gen6 SSDs will require liquid cooling?

Avi Shetty: At least in high-performance AI environments, particularly Nvidia-based deployments, we believe liquid cooling will be necessary.

Next-generation SSDs: PLC NAND

Anton Shilov: Will future NAND generations include both TLC and QLC? And what about PLC?

Avi Shetty: Never say never. We demonstrated PLC technology using floating gate NAND at the Flash Memory Summit several years ago. However, this business requires factory optimization and maintaining a manageable number of SKUs to maximize utilization and profitability.

That said, there absolutely will be opportunities for PLC. We have not announced any specific products or timelines, but there is active PLC development underway inside Solidigm.

Anton Shilov: That is interesting. However, PLC by itself only increases capacity by about 20% compared to QLC and at the same time requires significantly more sophisticated controllers and error correction.

Avi Shetty: That is true. However, those same concerns existed during every previous transition: from SLC to MLC, MLC to TLC, and TLC to QLC.

We were the first company to commercialize QLC NAND. Initially, many competitors questioned its value. Today, the industry increasingly recognizes the total-cost-of-ownership advantages that QLC provides, and multiple vendors now offer QLC products. I think the same process will occur with PLC.

It is also important to consider the broader market. Roughly 80% of storage capacity worldwide is still deployed on hard drives. PLC does not necessarily need to replace QLC on a one-to-one basis. Instead, it can create new opportunities where the advantages of solid-state storage — lower power consumption, higher density, smaller physical footprint, and lower total cost of ownership — become compelling.

You will likely see future solution development involving software partners that help address some of the limitations you are describing.

Anton Shilov: Do you expect retention characteristics to become a major challenge with PLC NAND?

Avi Shetty: Of course. PLC is a new technology, and retention characteristics will differ from what we see with QLC today.

The same is true across all NAND types. SLC, MLC, TLC, QLC, and eventually PLC all have different retention characteristics based on the underlying technology. The existence of those challenges does not mean we stop exploring future solutions. We will continue investing in that area.

Advanced packaging for NAND

Anton Shilov: As I mentioned, PLC only increases capacity by about 20%. Advanced packaging may ultimately have a much larger impact on SSD capacity. Could you discuss where packaging technology stands today and where it is headed?

Avi Shetty: Absolutely. Let me use our current products as an example. The 122TB SSD represents a significant packaging achievement. It is a U.2 drive with 48 NAND packages. Each package contains a 22-die stack. Each die is a 1.33Tb QLC device. Those 22-die stacks are what enable us to reach 122TB in a standard form factor.

Packaging technology remains one of our core investments. We continue developing technologies that allow us to place more dies into each package and deliver higher capacities to customers.

Anton Shilov: What about increasing the number of dies per package?

Avi Shetty: That is one of the primary ways to increase density. You can either increase die capacity or increase the number of dies per package. We intend to pursue both approaches.

Anton Shilov: How many dies per package do you think remain practical?

Avi Shetty: Today we are at 22. Future products will go beyond that, although I cannot discuss specific numbers.

Anton Shilov: What did previous generations use?

Avi Shetty: Depending on capacity requirements, previous products used 4-, 8-, or 16-die stacks. Of course, we are talking about a single NAND package in each case.

Storage-Class Memory, Optane, and Nvidia's Storage Next

Anton Shilov: What about storage-class memory?

Avi Shetty: Like Optane?

Anton Shilov: Not necessarily Optane itself, but something similar — something faster than NAND flash, yet capable of offering significantly higher density than DRAM at a lower cost.

Avi Shetty: Understood. Let me frame it from the perspective of the problem we are trying to solve. If you are asking whether Solidigm is developing a storage-class memory technology similar to Optane, then the answer today is no.

What we are focused on is addressing the requirements emerging from Nvidia's Storage Next initiative. The fundamental challenge is bandwidth. HBM is extremely fast, but it is also expensive and difficult to scale economically. As AI systems continue to grow, the industry needs additional memory and storage tiers that provide greater capacity at lower cost. That creates demand for NAND-based solutions that remain non-volatile while delivering improved latency and bandwidth characteristics.

We have not made any public announcements regarding storage-class memory technologies, but we continuously evaluate future technologies and architectural approaches.

Anton Shilov: So you are exploring concepts that could potentially bridge the gap between traditional NAND and memory?

Avi Shetty: We are evaluating a wide range of technologies that could help us continue delivering leadership products to our customers. When and if we have something to announce, we will do so publicly. At this point, however, we have nothing to disclose.

Anton Shilov: So storage-class memory is not currently a product category that Solidigm is actively pursuing?

Avi Shetty: If you are specifically referring to something similar to Optane, then no.

Optane was based on a fundamentally different technology. It was not NAND. It relied on a phase-change-memory-derived architecture and represented a completely different storage medium. We are not pursuing that type of technology today. What we are investing in is future NAND technology.

Anton Shilov: You think that future NAND technologies could eventually move closer to that space?

Avi Shetty: Exactly. Future NAND innovations could help narrow the gap between HBM, DRAM, and the next storage tier. That’s certainly one of the directions the industry is evaluating as AI systems continue to demand larger memory pools and greater bandwidth.

AMD has brought back its gaming champion from four years ago. The Ryzen 7 5800X3D has been revived in 2026 to breathe new life into the AM4 platform. The Zen 3-based CPU was the best CPU for gaming of its time, thanks to the first-generation 3D V-Cache technology. Since then, however, the competition in our CPU benchmark hierarchy has become more fierce.

Today's competition is Intel’s Core i7-14700K, based on the Raptor Lake Refresh architecture. At the time the Ryzen 7 5800X3D released, Intel’s 12th-gen Alder Lake CPUs were its main competition. Here, we revisit the comparison with Intel’s newer Core i7-14700K, which is available around the same price of $350.

The focus of this faceoff is to determine which CPU is the superior all-around chip. We will put the two CPUs through a series of tests spanning different categories to ultimately determine which CPU you should buy for your system.

This faceoff breaks down how two CPUs compare to each other in a head-to-head battle. If you'd like to read more about either processor, as well as see our full suite of tests, make sure to read our AMD Ryzen 7 5800X3D re-review and Core i7-14700K faceoff.

Features and Specifications: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

The Ryzen 7 5800X3D was first launched in April 2022 as a part of the Vermeer desktop CPU family. It is based on the Zen 3 architecture and built on TSMC’s 7nm production process. The CPU features 8 cores and 16 threads, with a TDP of 105W and a PPT of 142W. It has a base clock of 3.4 GHz and can boost up to 4.5 GHz.

The 5800X3D only supports DDR4 memory at a rated speed of 3200 MT/s over a dual-channel interface. It is compatible with the AM4 socket, with support for 300-series, 400-series, and 500-series AMD chipsets (though check support with your specific motherboard). It also supports 20 lanes of PCIe Gen 4. However, the 5800X3D does not have integrated graphics.

On a more positive note, the Ryzen 7 5800X3D was the first CPU to employ the new 3D V-Cache technology. As a result of stacking the cache vertically on the die, the 5800X3D has a total L3 cache of 96 MB. Of this pool, 64 MB is part of the 3D V-Cache stack. Core overclocking is disabled on the Ryzen 7 5800X3D due to its 3D V-Cache layout; DRAM overclocking still remains available.

Its competitor, Intel’s Core i7-14700K, uses a vastly different layout. It features the Raptor Lake Refresh architecture, which is a refined version of the 13th-generation Raptor Lake base architecture. The Core i7-14700K was launched in October 2023 and was built on a 10nm production process (Intel 7).

Intel’s 14th-generation CPUs use a hybrid core layout with performance-focused “P-cores” and more efficient “E-cores.” The 14700K also follows this structure, featuring 8 P-cores and 12 E-cores, for a total of 20 cores. In the 14700K, Hyper-Threading is only available on the P-cores, so the CPU has a total of 28 threads. The chip can boost the P-cores up to 5.6 GHz, while the E-core boost clock is 4.3 GHz.

Interestingly, the Core i7-14700K supports both DDR4 and DDR5 memory at 3200 MT/s and 5600 MT/s, respectively. The CPU is compatible with the LGA 1700 socket featured in the 600-series and 700-series Intel motherboards. There is also support for 16 PCIe Gen 5 lanes and 4 PCIe Gen 4 lanes.

The Core i7-14700K has a TDP of 125W, with a higher PL2 limit of 253W. Integrated graphics are also offered in the 14700K in the form of UHD Graphics 770. There is 33MB of shared L3 cache on the chip. Perhaps more importantly, the Core i7-14700K is fully unlocked for overclocking, which is a big advantage over its competitor for today, though that requires a Z-series motherboard.

Zooming out a bit, it is clear that the Core i7-14700K is vastly superior to the Ryzen 7 5800X3D on paper. It is a newer CPU, so it has a better feature set, including PCIe Gen 5 and DDR5 support. It offers more cores, a higher boost clock, integrated graphics, and an unlocked multiplier for overclocking.

⭐Winner: Intel Core i7-14700K

Nothing is decided on paper alone, but the Core i7-14700K offers much better specs, newer features, and even has overclocking support. It takes this round quite easily.

Gaming Benchmarks and Performance: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

AMD claims to have “re-engineered” the Ryzen 7 5800X3D for its 2026 re-release, so we have tested it again, along with a whole bunch of worthy competitors, including the 14700K. We chose the 1080p resolution for our 16-game test suite in order to maximize the performance differences between the various CPUs. The graphics card used was the GeForce RTX 5090 to keep potential GPU bottlenecks to a minimum. Let’s get into the results.

Starting off with our 16-game FPS geomean at 1080p, the Core i7-14700K dominates the Ryzen 7 5800X3D with an average result of 166.7 FPS across our tested games, compared to the 145.6 FPS result of the Ryzen 7 5800X3D. That is a 14.5% difference in favor of the 14700K in our performance geomean. In 1% lows, the 14700K leads the Ryzen 7 5800X3D by 20% on average, putting out 114 FPS against the Ryzen’s 95.

However, there is another side to this benchmark table. The Core i7-14700K supports both DDR4 and DDR5 memory, so we tested it in both configurations. With DDR4-3200 memory, the 14700K’s advantage vanishes, and instead the Ryzen 7 5800X3D leads by 1.04%, or just 1.5 FPS. The 1% lows are in favor of 14700K by only 3 FPS (3.15%), which is astonishingly close.

When the Intel CPU is paired with DDR5 memory, the Ryzen 7 5800X3D’s cache advantage seems to be struggling against the Core i7-14700K’s raw core count and higher boost clock (along with far faster memory speeds). Looking at individual titles, we see a similar pattern with the Core i7-14700K holding a consistent lead over the 5800X3D.

In 007 First Light, the 14700K paired with DDR5 memory has a 25.7% lead on average over the 5800X3D. That lead shrinks to 21.5% in Crimson Desert, and the difference is 13.7% in favor of the 14700K in Cyberpunk 2077. Interestingly, the Core i7-14700K leads the entire pack in Flight Simulator 24, establishing a 26.6% lead over the 5800X3D in this title. The DDR5-equipped 14700K also leads the 5800X3D in Spider-Man 2, Starfield, The Last of Us Part One, Baldur’s Gate 3, and Counter-Strike 2.

However, when the Core i7-14700K is paired with DDR4-3200 memory, the picture changes completely. The Ryzen 7 5800X3D leads the i7-14700K with DDR4 memory in Baldur’s Gate 3 by 11.7%. In Crimson Desert, the lead is 3.2% for the 5800X3D, and 2.6% in Cyberpunk 2077. The Ryzen 7 5800X3D sits between the DDR5 and DDR4 versions of the 14700K in a few other titles, including Counter-Strike 2 and DOOM: The Dark Ages.

There are also some titles in which the Ryzen 7 5800X3D leads both the DDR4 and DDR5-equipped versions of the Core i7-14700K. In F1 2024, the Ryzen 7 5800X3D leads the DDR5 14700K by 5.6%, and the DDR4 14700K by 13.7% on average. The same pattern can be seen in Final Fantasy XIV, with a 6.6% lead over the 14700K using DDR5 memory, and in Minecraft RT, with a 18.5% lead over the 14700K using DDR4 memory.

It is certainly all over the place when you put both configurations of the 14700K into the mix, but the two behave more like separate CPUs. The long and short of it is that the 14700K with DDR5 memory provides the best gaming performance on average, followed by the Ryzen 7 5800X3D. The DDR4-equipped 14700K is ever-so-slightly slower than the 5800X3D, but it really just depends on the game you’re playing.

During our testing, the Core i7-14700K averaged 4.93 GHz with DDR5 memory and 4.88 GHz with DDR4 memory. The Ryzen 7 5800X3D could only manage 4.34 GHz, but it sipped only 77.5 watts during our gaming tests. The 14700K DDR5 averaged 132.4 watts, while the DDR4-equipped 14700K averaged a whopping 155.1 watts during gaming. This is why the 14700K with DDR4 reached an average temperature of 80 °C, compared to 62 °C for the 14700K with DDR5 and 59 °C for the 5800X3D.

In addition to running the coolest, the Ryzen 7 5800X3D is also the most efficient CPU of the bunch. The 5800X3D had an FPS-per-watt output of 1.88, compared to 1.26 for the Core i7-14700K with DDR5 memory, and just 0.93 for the DDR4 version. It is amazing how much the Core i7-14700K suffers when paired with DDR4 memory.

Lower overall performance also hurts the value proposition of the DDR4-equipped 14700K, as it puts out just 0.39 FPS-per-dollar, compared to the 0.45 of the DDR5-equipped 14700K. Astonishingly, the Ryzen 7 5800X3D falls between the two 14700K versions, delivering 0.42 FPS per dollar. This makes the Core i7-14700K the value king, but only if you pair it with DDR5 memory. I suspect that will be tricky in the current market.

⭐Winner: Tie

While the Ryzen 7 5800X3D does slightly pull away from the DDR4-equipped 14700K, both of these setups get demolished by the 14700K when it is paired with DDR5 memory. We're calling this round a tie considering the massive price disparity between DDR4 and DDR5 memory right now.

Productivity Benchmarks and Performance: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

Productivity performance spans single-threaded and multi-threaded workloads, so we tested the CPUs across a range of benchmarks covering both categories. Just like in our gaming tests, we tested the 14700K with both DDR5 and DDR4 memory, since it does impact the performance significantly.

Intel’s hybrid architecture has historically been quite strong at multi-threaded workloads due to E-cores, and that pattern appears here too. In our multi-threaded performance ranking geomean, the Core i7-14700K scores 492 points, a massive lead of 116.7% over the Ryzen 7 5800X3D that could only manage 227 points on average. Even when the Core i7-14700K is paired with DDR4 memory, it has a 105% higher average score than the Ryzen 7 5800X3D.

The superior core count of the 14700K is proving to be the difference maker in this category. In the Cinebench 2024 multi-core test, the 14700K with DDR5 memory is a whopping 126.6% faster than the Ryzen 7 5800X3D. Even the DDR4-equipped 14700K secures a 107% lead over the 5800X3D in Cinebench. The lead for the 14700K is about 137% in POV-Ray, and it shrinks to 135% when using DDR4 memory.

Blender tests were also favorable for the 14700K, but we didn’t see a big difference between DDR4 and DDR5 systems in these benchmarks. In Junkshop, the DDR5-equipped 14700K leads the 5800X3D by 116.4%; in Monster, by 116.6%; and in Classroom, by 118.3%. The DDR4 variant follows closely behind, by 1 or 2 percentage points.

The memory generation again comes into play when we look at HandBrake x265 10-bit encoding, with the DDR5-14700K leading the 5800X3D by 90.5%, while the DDR4-14700K manages a 82% lead. The gap is even larger in x264 encoding, with the DDR5 variant gaining a 105% lead over the 5800X3D, while the DDR4 variant can only manage a 63% lead.

That still makes the Core i7-14700K far better than the 5800X3D in productivity workloads, regardless of the memory generation. However, we still have single-threaded results to look at. Our single-threaded performance ranking geomean puts the Core i7-14700K 36.6% faster on average than the Ryzen 7 5800X3D. Interestingly, there is no difference in single-threaded performance between the DDR5 and DDR4 variants of the 14700K.

The same trend is seen in individual benchmarks as well. The 14700K is about 25% faster than the 5800X3D in Lame’s audio encoding test, and the DDR4 variant is in the same ballpark as well. Curiously, the DDR4-equipped 14700K is slightly faster than the DDR5-14700K in Cinebench 2024 and also outperforms the 5800X3D by 36.6%. Safe to say, the RAM difference doesn’t really come into play in these tests.

Overall, though, the winner is quite clear. The Ryzen 7 5800X3D is a gaming-oriented chip with only 8 cores and 16 threads, so it is no match for the 20-core 14700K in productivity workloads. Whether you go for DDR4 or DDR5 is your decision, but the productivity champion of this faceoff is the Core i7-14700K.

⭐Winner: Intel Core i7-14700K

With an average lead of 116% over the Ryzen 7 5800X3D in multi-threaded tasks, the Core i7-14700K sweeps the productivity round quite easily.

Overclocking: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

Overclocking has never been a strong suit of AMD Ryzen processors; however, the Ryzen 7 5800X3D doesn’t support core overclocking at all. AMD cited the 3D V-Cache technology as the reason the 5800X3D can’t be overclocked, and they were right to assume so.

Due to the vertically-stacked cache, heat transfer from the CPU die to the heatspreader was a real issue. An overclocked 5800X3D would have sipped more power and produced more heat. Therefore, an efficient heat-transfer system was needed but could not be developed in time for the first-generation V-Cache product.

AMD has since reinstated overclocking support for Ryzen 9000 series X3D CPUs by flipping the cache layout, so it no longer hinders heat transfer. However, the Ryzen 7 5800X3D’s core multiplier still remains locked, but you can still tune the DRAM and Infinity Fabric clocks.

The Core i7-14700K, on the other hand, is tailor-made for overclocking. Being a K-series SKU, the 14700K comes with an unlocked multiplier and all the Intel bells and whistles for overclocking. It can reach 6.1 - 6.2 GHz on individual cores with proper cooling, and users can expect a 5.6 - 5.8 GHz all-core overclock on most setups.

Its overclocking toolkit features traditional multiplier adjustments, voltage controls, and established BIOS interfaces that most enthusiasts are already familiar with. The Core i7-14700K also has a significant amount of power headroom to play with, although temperatures become a concern as soon as the power consumption ramps up.

By all overclocking metrics, the Core i7-14700K is the superior CPU for tinkerers. The Ryzen 7 5800X3D can’t be manually tuned, at least not in the traditional sense, and therefore doesn’t really stand a chance in this round.

⭐Winner: Intel Core i7-14700K

The 14700K is the real deal when it comes to overclocking support. The Ryzen 7 5800X3D is locked and therefore can’t be overclocked, so Intel sweeps this round.

Power Consumption and Efficiency: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

The Ryzen 7 5800X3D has a base TDP of 105W and a PPT of 142W. Intel’s is much higher, with the 14700K clocking in at 125W TDP and a PL2 limit of 253 watts. However, TDP numbers don’t give us a good idea of real-world power consumption, so we ran our own detailed tests.

First, at idle, the 5800X3D consumed only 5 watts, while the 14700K consumed 27 watts. In an active-idle situation, such as YouTube playback, the Core i7-14700K consumed 28 watts with DDR5 memory and a concerning 39 watts with DDR4 memory. The 5800X3D, on the other hand, sipped only 9 watts, making it anywhere from 67% - 76% more efficient than the 14700K.

Moving on to all-core workloads, in our y-cruncher multi-threaded AVX power test, the Ryzen 7 5800X3D consumes 119 watts, while the Core i7-14700K clocks in at a staggering 335 watts, a 181.5% higher figure. Even the Core i7-14700K with DDR4 memory consumed 307 watts, which is still a 158% increase over the 5800X3D’s power consumption.

In Linpack, the Ryzen 7 5800X3D is again more reserved, with the 14700K consuming 168.6% more power than the Ryzen. The DDR4 setup was not much better, with a 137.2% higher power consumption than the 5800X3D in this test. The gap widens even more in Cinebench 2024’s multi-core render and our Blender tests, which show the 14700K consuming anywhere from 250% to 285% higher power than the 5800X3D.

In our encoding tests, the situation remains pretty much the same. In Handbrake x264, the DDR5-14700K consumed 242% more power than the 5800X3D, while the DDR4-14700K consumed nearly 200% more. Similar numbers were seen in Handbrake x265 and SVT_AV1 encoding, with the 5800X3D being the clear winner.

We even looked at single-threaded workloads to determine the power consumption of those tasks. In y-cruncher’s single-threaded AVX power test, we saw the 14700K consume 157% more power when paired with DDR5 memory, and 132% more when using DDR4 memory. Safe to say, the Intel CPU does not fare any better in these workloads either.

To determine the efficiency, we calculated the watts-per-FPS number in Handbrake x265. The 5800X3D was 43.4% more efficient than the 14700K with DDR5 RAM, and about 41% more efficient in this task than the 14700K with DDR4 memory. The pattern can again be seen in Cinebench 2024’s efficiency test, where we look at points-per-watt. The 5700X3D is anywhere from 62% to 68% more efficient than the 14700K in this task.

We can also visualize the efficiency differences using our handy scatter plots. In the Linkpack power efficiency plot, the 5800X3D is towards the bottom left of the chart, while the 14700K is more towards the top. This means that the 14700K uses substantially more energy to deliver marginally higher performance than the 5800X3D. Ideally, you want to be towards the bottom right of this graph.

So, the Ryzen 7 5800X3D consumes much less power in both single-threaded and multi-threaded productivity workloads, and as we saw in our gaming tests, it runs cooler as well. The Core i7-14700K has a distinct performance advantage in all-core workloads, but the power consumption ramps up quickly once it gets going. Still, the Ryzen 7 5800X3D is the clear winner in this round.

⭐Winner: AMD Ryzen 7 5800X3D

The Ryzen 7 5800X3D consumes between 150% and 300% less power than the Core i7-14700K in all-core workloads, making it the definitive winner in this round.

Pricing: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

The pricing situation is a bit of a wildcard in this comparison, since these are not exactly “new” CPUs. The Ryzen 7 5800X3D was recently re-released at $350, which is $100 lower than its 2022 price tag. The Core i7-14700K is currently priced at $370 at the time of writing, which makes the 5800X3D $20 cheaper in a direct comparison.

However, comparing the two CPUs is more than just comparing their sticker price. We must also look at the platform costs of the two CPUs. The Ryzen 7 5800X3D uses the fan-favorite AM4 socket, which has a whole heap of chipsets in all price brackets. You can pair the Ryzen 7 5800X3D with a mid-range B550 or a high-end X570 motherboard, but older 400-series motherboards are also compatible, depending on the board.

As far as the price goes, B550 motherboards can be purchased for $80 - $180, while higher-end X570 motherboards range from $150 - $300. Some premium models can even go beyond $400, but those are not really needed for our CPU since it doesn’t support overclocking. A nice mid-tier B550 or X570 motherboard will be more than enough for our needs.

Memory is where the price difference really grows. The Ryzen 7 5800X3D only supports DDR4 memory, so it is relatively safe from the ongoing DRAM crisis. A nice 32GB DDR4-3200 kit can run you about $140 - $160, which is definitely higher than DDR4 prices of the past, but nothing compared to current DDR5 rates. The Ryzen 7 5800X3D also needs an aftermarket cooler since it doesn’t come with one, and that can cost you about $100 - $150 too.

For the Core i7-14700K, you have the option of either a DDR4 or a DDR5 motherboard. Even then, you still have to choose between a 600-series or a 700-series chipset. For the sake of this comparison, let’s go with a Z790 motherboard since the 14700K is unlocked and we want those overclocking capabilities. A basic Z790 motherboard can be found around the $150 mark, but we would want to go with something that has decent VRMs. That can cost around $200-$250 at current prices.

Of course, as evidenced in our benchmarks, DDR5 memory is the best way to maximize the 14700K's performance. Due to the RAMpocalypse, DDR5 memory is ridiculously expensive, and a 32GB DDR5-6000 kit can cost between $390 - $550 at the time of writing. Going with DDR4 would require a motherboard swap, but it would save you between $300 and $350 on the system based on these two components alone.

For cooling, the 14700K requires special consideration, as we have the option to overclock. Even a stock 14700K sips more power and produces more heat than a 5800X3D, but if you plan to overclock, the thermals can get out of hand pretty quick. You’ll ideally use a solid 360mm AiO liquid cooler for the 14700K, which can add about $100 - $150 to the cost of your build.

Another factor to consider when determining the value of a CPU is the longevity of its platform. AMD’s AM4 platform has been going strong for a decade, and AMD has continued to support it through updates and releases such as the 5800X3D. However, it would be hard to see AMD releasing more CPUs for the AM4 platform going forward.

On the other hand, Intel’s LGA 1700 socket was already semi-retired, but new reports suggest that Intel will bring this platform back in early 2027. New “Raptor Lake Next” CPUs will reportedly be available on the same socket and the same motherboards, so there is certainly a better upgrade path on Intel’s side.

When we put everything together, the Core i7-14700K is a bit hard to recommend from a value perspective. The motherboards for the 14700K are more expensive on average, and if you want to maximize its performance, you will have to take a massive hit to your wallet with DDR5 memory. Moreover, it is more expensive to cool, too. Its platform looks more future-proof in light of recent rumors, but that can’t guarantee it a win in this round.

⭐Winner: AMD Ryzen 7 5800X3D

The 5800X3D is cheaper to get up and running, since you only need an affordable B550 motherboard and some DDR4 memory to get started. The 14700K can be cheap, but that requires you to leave serious performance on the table and go with a DDR4 setup.

Bottom Line: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

After a grueling 6-round back-and-forth, we finally have our winner. The Intel Core i7-14700K is the superior CPU of the two. Now, it is not as black-and-white as the 4-3 score might suggest, but the 14700K is still the winner of this faceoff.

The Core i7-14700K delivers better gaming performance on average than the 5800X3D. Sure, there are some titles that favor AMD’s 3D V-Cache, but those wins were not as frequent. However, AMD’s 5800X3D has a better chance if the 14700K is limited by DDR4 memory.

Intel’s 14700K is also vastly superior in productivity and has support for manual overclocking. AMD’s main selling point for the 5800X3D in 2026 is its low price, both upfront and in terms of platform costs. It is also an easier CPU to maintain since it runs cooler and consumes less power.

Interestingly, the choice also depends heavily on your memory generation of choice. It is better to save a few bucks and go with a 5800X3D if you plan to stay on DDR4 for now. However, if you are willing to make the (difficult) jump to DDR5, the 14700K is the clear choice.

Potential buyers who want to stick to gaming should still prioritize a Ryzen 7 5800X3D over a Core i7-14700K with DDR5 memory. On the other hand, if you regularly run any type of productivity workload, the 14700K blows the Ryzen out of the water.

⭐ Winner: Intel Core i7-14700K

Nonetheless, the overall winner of our faceoff is Intel’s Core i7-14700K.

Check Out More CPU Faceoffs

• Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7800X3D
• Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 9700X
• AMD Ryzen 7 9850X3D vs AMD Ryzen 7 9800X3D
• Intel Core i7-14700K vs Intel Core Ultra 7 265K
• AMD Ryzen 9 9950X3D2 vs Ryzen 9 9950X3D

Servers running x86 processors from AMD and Intel used to rule the market, both unit and money-wise, less than a decade ago, but fast forward to today, Arm-based machines command well over 45% of the server market, according to data released by IDC. While technically x86 machines still control 52% of the market in terms of revenue, the real winner is a different category altogether: GPU- and ASIC/FPGA-accelerated systems, which generated over 70% of the global server revenue in the first quarter of 2026.

Server market reaches $122.6 billion in a single quarter, Dell leads the game

IDC estimates that the global server market generated a record $122.6 billion in revenue in the first quarter of 2026, up 30.4% year-over-year, as spending on AI infrastructure remained particularly strong.

Sales of ODM Direct servers — custom machines ordered by hyperscalers that run merchant or custom silicon — accounted for 50.2% of the revenue (down from 64.1% in Q1 2025) and reached $61.53 billion, up modest 2.1% year-over-year*. By contrast, sales of standard servers from well-known brands grew at a much higher pace, which suggests that branded vendors such as Dell, HPE, Supermicro, and others won a larger portion of AI infrastructure deployments than they did a year earlier. That was probably made possible by accelerating enterprise AI deployment and sovereign AI projects, which tend to buy machines from branded vendors, as well as hyperscalers increasingly turning to well-known suppliers for AI hardware.

When it comes to vendor rankings, Dell remained the largest server supplier by revenue with a 16.5% share of the market after its revenue surged 244.1% year-over-year to $20.3 billion, which was driven by exceptionally strong AI server demand. Supermicro remained in second place with $9.3 billion in revenue and a growth of 128.9%.

Lenovo ranked third with $5.6 billion and 36.5% growth, while IEIT Systems (which is a part of the sanctioned Inspur Group) dropped to fourth after revenue declined 7.0% to $4.0 billion. HPE was No.5 with $3.7 billion in revenue, up 17.2%. Other vendors — from Asus to Atos and from ASRock Rack to Gigabyte — commanded 14.8% of the market with $18.11 billion in revenue, up from 13% and $12.21 billion in the same quarter a year ago.

Arm-based machines rapidly gain revenue share

As AI servers dominated the market in Q1 2026, systems with various types of accelerators accounted for over 70% of the revenue. However, the rise of Arm-powered machines is the elephant in the room that is hard to miss, as it represents a tectonic shift in the whole market, both to the Arm instruction set architecture (ISA) in general and custom-built Arm CPUs designed by hyperscalers.

Non-x86 platforms generated $58.7 billion in revenue, a 107.6% increase year-over-year, which lifted their share of the market to 47.9%. Most of the non-x86 systems are Arm-based AI machines (think Nvidia's NVL72) as well as systems running custom CPUs, AWS, Google, and Microsoft, just to name a few. Still, also keep in mind IBM Z mainframes and IBM Power Systems (including storage) that use CPUs featuring proprietary non-x86 and non-Arm ISAs and which still generate $1 billion or more in revenue. IDC claims that Arm-based machines accounted for more than 95% of non-x86 revenue, so it is safe to say that Arm-based machines commanded over 45% of server revenues in Q1 2026.

One of the reasons why Arm-based machines now command a huge chunk of the server market is because they are used inside such systems as Nvidia's NVL72 'Blackwell' that sell for up to $6.5 million per unit. Each NVL72 rack-scale solution carries 36 compute trays with two Blackwell GPUs and one Grace CPU per unit, so while unit-wise each we are only talking about 36 processors, dollar-wise one NVL72 machine is as expensive as 928 entry-level 1P server (for $7,000) for cloud or edge applications or 433 higher-end 2P servers (for $15,000) for cloud or virtualization applications.

Given the fact that Nvidia will continue bundling its own Arm-based Vera CPUs with NVL72 'Vera Rubin' machines that will be more expensive than their Blackwell ancestors, we will not be surprised that Arm-based machines will account for well over 50% of the server market revenue in the second half of this year or in 2027. Also, keep in mind that Nvidia plans to sell server racks featuring only Vera CPUs for agentic AI applications, which will further drive sales of Arm-based machines.

Accelerated servers: The real winner

Since AI servers dominate server sales, it is not surprising that sales of accelerated servers are increasing. Systems equipped with GPUs produced $68.9 billion in revenue during the quarter (up 24.8% compared to the same period a year earlier) and accounted for 56.2% of all server sales. Servers based on other accelerator types, including custom ASICs and FPGAs, expanded to $17.7 billion, up 122.1% YoY. As a result, accelerated servers earned $86.6 billion in Q1 2026, which is around 70.6% of all server revenue.

X86 servers remain unit volume champions, but suffer from shortages

In contrast, x86 server revenue declined 2.9% to $63.9 billion, though IDC attributes this weakness to supply limitations rather than deteriorating demand. The market research firm claims that the industry's primary constraint is no longer customer appetite for general-purpose servers, but rather the availability of key components, including CPUs, DRAM, NAND memory, and hard drives.

Without any doubt, x86 servers remain working horses for the industry. In fact, many of them use accelerators, including ASICs, FPGAs, and GPUs, as they are used for a wide range of workloads, including AI, supercomputing, simulations, encryption, video transcoding, and many more.

AMD and Intel shipped nearly 20 million EPYC and Xeon SP processors for data center systems in 2025, according to Dean McCarron, the head and principal analyst at Mercury Research. He believes Nvidia is on track to ship four million Grace and Vera CPUs this year, which is considerably lower compared to shipments of AMD and Intel. It is hard to estimate how many custom Arm-based CPUs are deployed by AWS, Alibaba, Google, and Microsoft, but it is safe to say that we are talking millions of CPUs here; otherwise, the companies would not be able to justify development and production of custom silicon.

From a volume perspective, x86 servers remain the most popular machines, and it will probably take some time before ARM can challenge x86 in mainstream general-purpose servers. Nonetheless, it is safe to say that Arm-based data center CPUs are catching up with x86 parts in terms of volumes.

Summary

The global server market hit a record $122.6 billion in the first quarter of 2026 as AI infrastructure spending continued. Accelerated systems powered by GPUs, custom ASICs, and FPGAs generated more than 70% of server revenue, while Arm-based platforms — including Nvidia's Grace Blackwell as well as custom CPUs from Arm, Google, and Microsoft — captured nearly half of the market.

Although x86 servers based on AMD EPYC and Intel Xeon processors remain dominant in shipment volumes, supply shortages of CPUs, memory, and storage components constrained revenue growth, which further enabled Arm-powered AI-optimized systems to gain share. But while at 20 million data center processors per year, x86 volumes are untouchable for Arm today, things may change in the coming years. Nvidia is on track to ship 4 million CPUs in 2026, and other developers of custom Arm-based CPUs are certainly not standing still.

*There is one significant difference with IDC's 'ODM Direct' classification. IDC classifies revenue according to which company invoices the customer, not necessarily who manufactures the hardware. As a result, while many AI servers are built by ODMs like Compal, Foxconn, or Quanta, they are sold under brands like Dell or HPE. As a result, while the latter get more business from enterprises or sovereign AI deployments, this does not mean that big ODMs are losing business; they are actually gaining it, as the appetites of hyperscalers like AWS, Google, Meta, or Microsoft are not going anywhere, just demand from new entrants emerges.

Intel has appointed Seok-Hee Lee, the former chief executive of memory maker SK hynix and battery maker SK On, as executive vice president of Intel Foundry, handing the semiconductor veteran control of advanced packaging, system integration, and all back-end technology development and manufacturing. Lee reports directly to CEO Lip-Bu Tan, and his arrival comes with a structural change at the foundry: Intel is splitting advanced packaging out as a dedicated business, with Naga Chandrasekaran narrowing his focus to front-end work on the Intel 18A and 14A nodes. Longtime executive Navid Shahriari is retiring after 37 years, the company announced.

Lee spent roughly a decade at Intel earlier in his career before holding leadership roles across the Korean chip industry, including the top job at SK hynix, one of the world's two largest suppliers of high-bandwidth memory. Tan credited Lee with "deep expertise in leading complex, high-scale technology and manufacturing organizations," and said the hire would help Intel "tightly couple leading-edge logic, memory, networking, and other components" for foundry customers.

Putting a former memory chief over packaging aligns with where Intel's back-end ambitions are. HBM stacks sit alongside logic dies inside the same package on every modern AI accelerator, and it’s joining those two components together that Lee now oversees. Last month, it was reported that SK hynix was testing Intel's EMIB packaging for HBM integration, sending both companies' shares higher.

Tan named EMIB-T and HBI as the technologies Intel intends to ramp to high volume under Lee. EMIB-T adds through-silicon vias to Intel's embedded bridge for higher power delivery and HBM4-class bandwidth, and is rolling out in production fabs this year. Intel has positioned the EMIB family against TSMC's CoWoS, whose lines have been oversubscribed for more than two years, and is reportedly in talks with Google and Amazon to package their custom AI chips.

It goes without saying, then, that the stakes for the unit Lee’s inheriting are huge. Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and CFO David Zinsner has said packaging revenue could exceed $1 billion at gross margins near 40%, with prepaid hyperscaler commitments reaching into the billions. Korean trade press, including the Seoul Economic Daily, has spun Lee's appointment around Intel's difficulty securing yields on its proprietary back-end processes, the kind of high-volume manufacturing problem he managed for decades in memory.

The hire follows Intel's April recruitment of Samsung foundry veteran Shawn Han. Lee resigned from SK On on May 28th, citing health reasons, according to Korean outlets, only to return to the industry three weeks later.

President Donald Trump said on Thursday that Apple has agreed to work with Intel to “design and build” chips in the United States, posting the claim to Truth Social before either company confirmed any arrangement. Apple and Intel didn’t respond to initial requests for comment from Reuters, and neither has issued a statement acknowledging a finalized deal.

Trump says the deal is part of his administration’s push to reshore semiconductor manufacturing, writing that the U.S. needs to build its chips domestically and that he "decided to help Intel because we need to design and build our Chips right here in America.” He credited earlier government intervention for drawing Nvidia and Elon Musk's TeraFab project to Intel's foundry.

Apple already designs its own silicon and has done so since it dropped Intel processors from its products in 2020. Any arrangement here would purely be a foundry deal, with Intel acting as a contract manufacturer for chips Apple designs in-house. It wouldn’t return Apple to Intel-designed processors, and it certainly wouldn’t displace TSMC from Apple's flagship products.

The logic behind any such deal for Apple would be simple supply diversification; the company remains dependent on TSMC, whose leading-edge capacity is being absorbed by AI customers, including Nvidia and AMD. Placing a lower-volume part on a second source reduces single-foundry exposure without touching the iPhone and high-end M-series lines that rely on TSMC's most advanced nodes.

We’ve known about much of this for a little while now. Reporters caught wind of a preliminary deal last month, following discussions that ran for more than a year. Before that, analyst Ming-Chi Kuo and GF Securities outlined the likely scope: Apple's M7 SoC built on Intel's 18A-P process, powering the MacBook Air and entry-level iPad Pro, with mass production targeted for late 2027.

Those two product tiers accounted for roughly 20 million units in 2025, with annual shipments expected to settle between 15 million and 20 million — significant for a new foundry customer, but small enough to leave TSMC's revenue mix intact. Reporting has also suggested that Apple's A21 iPhone chips will move to Intel's 14A node around 2028, but none of this has been confirmed by Apple or Intel.

Trump's announcement comes just two days after Intel said its 18A-P process had entered risk production, announced at the VLSI Symposium in Honolulu. The node is the first performance-enhanced version of 18A, and Intel claims it delivers 9% higher performance at the same power, or 18% lower power at the same performance, while staying design-rule compatible with 18A so customers can reuse existing IP. CEO Lip-Bu Tan told investors last month that he expects multiple foundry commitments to close in the second half of 2026.

Intel has yet to confirm a single leading-edge customer for 18A, and any commitment from Apple would be a best-case scenario in terms of securing the validation the company both desperately wants and needs. The U.S. government holds a 10% stake in Intel, and its shares rose as much as 9% in premarket trading on the news, extending a run that has lifted the stock 464% over the past 12 months to a market cap of $608.7 billion.

This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity. In the space of 12 months, Intel has gone from canceling fabs to running short of them. In July last year, the company scrapped a planned €30 billion megafab in Magdeburg, Germany, and a $4.6 billion assembly and test plant near Wroclaw, Poland, citing a lack of committed demand. Then, in April this year, it paid Apollo $14.2 billion to repurchase the 49% stake in its Ireland fab that it had sold for $11.2 billion in 2024. Three weeks later, CFO David Zinsner described "unprecedented demand for silicon" alongside Q1 results that sent the stock up 24% in a single session, its best day since October 1987.

The next round of capacity development now hinges on two key deadlines: CEO Lip-Bu Tan told investors in January that prospective 14A customers will begin to make firm supplier decisions "starting in the second half of this year and extending into the first half of 2027." Separately, the enhanced 35% advanced manufacturing investment credit signed into law last July applies only to fab construction that begins before December 31st, 2026; projects that break ground in 2027 get nothing.

Both clocks run out within months of each other, and both bear on the same construction projects.

Arizona

Fab 52 at the Ocotillo campus in Chandler is the production foundation for everything on Intel's 2026 to 2028 product roadmap. The facility became fully operational in October last year as the first high-volume home of Intel 18A, building Panther Lake compute tiles and, later this year, Clearwater Forest. Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is "capable of more than 10,000 18A wafer starts per week," which works out to roughly 40,000 wafer starts per month at full ramp and makes it larger than TSMC's Fab 21 phase 1 and phase 2 combined.

That’s named capacity, however, not current output; Intel has indicated that 18A yields will reach industry-standard levels in early 2027, and until then, the company is capping CPU output on the node, leaving part of Fab 52's capacity idle. Tan said in May that 18A yields are improving by 7% to 8% per month.

Fab 62, the second from Intel's $20 billion 2021 Arizona expansion, is expected to be ready around 2028. Intel hasn’t officially assigned it a node, leaving it open as a stopgap for 14A if Ohio isn't ready, or as additional 18A capacity if external demand comes sooner. Brookfield Infrastructure put up to $15 billion into the two Chandler fabs in 2022 for a 49% share of the joint venture, and unlike the Apollo arrangement, Intel has made no move to buy that stake back, so every wafer out of Fab 52 and Fab 62 will have revenue share commitments attached to it.

Oregon

As the home of 14A, D1X complex at Gordon Moore Park in Hillsboro — a low-volume fab and development site — is currently the only place Intel develops leading-edge process technology, with Chandrasekaran telling CNBC the node will be developed first in Oregon, with a goal of risk production in 2028 and high-volume manufacturing in 2029.

Hillsboro houses Intel's High-NA EUV machines, including the first ASML Twinscan EXE:5200B system delivered anywhere, and 14A is the first Intel node designed around it. Oregon also carried early 18A production while Arizona ramped up. Intel began permitting work in February 2024 for a multibillion-dollar expansion of the campus following the approval of an air quality permit, though no construction start has been announced to date.

Ohio One

Ohio is Intel’s most problematic fab project on paper. It broke ground in New Albany way back in 2022 on a $28 billion first phase, originally targeting 2025 production. In February 2025, however, Chandrasekaran reset its schedule, targeting 2030 for the completion of Mod 1 with operations between 2030 and 2031, and Mod 2 in 2031 with operations in 2032. In a memo setting out this new schedule, Chandrasekaran said Intel preserves “the flexibility to accelerate work and the start of operations if customer demand warrants.”

Spanning nearly 1,000 acres, the site is designated for 14A and future nodes, and has room for up to eight fabs. Intel has spent roughly $5 billion there to date as of March 2025, including $1.4 billion in total for that year. Bechtel, the lead contractor, posted a wave of new construction job listings in January, the same month Tan declared Intel is “going big time into 14A.”

Still, customers (or a lack thereof) remain the gating factor for 14A production. Intel told investors in January that it’s got two prospective customers evaluating 14A test chips, and its SEC filings still warn that without a significant external customer, it “may pause or discontinue” 14A, successor nodes, and various manufacturing expansion projects.

Elon Musk said in April that his planned TeraFab project — the first named taker for the node — will use 14A process technology to make AI chips, though test production is expected to be years out. This also isn’t such a big win in terms of the volume commitment Intel’s filings say it needs for 14A to be viable. At the time of writing, 14A’s next and arguably most critical milestone is the 14A v0.9 PDK, which Tan says will reach external customers in October.

"The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Ireland and canceled projects

Launched in 2023, Fab 34 in Leixlip is Intel's only EUV-class site in Europe, producing Intel 4 and Intel 3 silicon for Core Ultra and Xeon 6 parts. In 2024, Apollo-managed funds paid $11.2 billion for a 49% interest in the joint venture entitled to the fab's output, a deal that gave Intel a much-needed cash injection at the time.

In April this year, Intel bought that stake back for $14.2 billion — at a premium of roughly 27% — funded from cash and about $6.5 billion in new debt issuance. Apollo walked away with around $3 billion in return for two years of exposure, and Intel paid a nine-figure annual cost of capital to reclaim needed wafer revenue.

“Flexibility and alignment are core to how we approach relationships as a long-term, solutions-oriented capital partner, and we are pleased to facilitate this transaction in support of Intel's evolving strategic and operational priorities,” said Apollo Partner Jamshid Ehsani at the time.

Magdeburg, once pitched as a €30 billion home for 14A-era production with roughly €10 billion in German subsidies attached, was postponed to 2029-2030 in November 2024. This prompted the German government to reallocate those subsidies to the federal budget and, following a $3.2 billion operating loss with Q2 2025 financial results, Intel killed the project, the subsidies dying with it.

Wroclaw's $4.6 billion assembly and test plant was canceled the same day, and Costa Rica's assembly and test operations were consolidated into Vietnam and Malaysia. Fab 38 in Kiryat Gat, Israel, the planned $25 billion expansion announced in 2023 with $3.5 billion in Israeli government backing, has been paused for the last two years, with no restart announced. Every leading-edge wafer Intel produces for the foreseeable future will come therefore come from three U.S. states and one campus in Ireland.

Packaging and test

Fab 9 in Rio Rancho, New Mexico, a $3.5 billion conversion that opened in January 2024, is the only high-volume Foveros 3D stacking site in the United States. Foveros is the packaging behind every tiled Intel design since Meteor Lake, bonding compute, graphics, and I/O dies vertically rather than laying them side by side, and it is integral to the stacked Clearwater Forest parts now ramping on 18A.

Intel runs it alongside the neighboring Fab 11x as a single co-located operation, which EVP Keyvan Esfarjani called “the only U.S. factory producing the world's most advanced packaging solutions at scale.” The buildout created hundreds of Intel jobs and more than 3,000 construction roles, and the campus later drew a further $500 million in CHIPS funding for modernization.

The $7 billion Penang complex in Malaysia, placed on indefinite hold in early 2025, has been revived: the buildout is now 99% complete, and first-phase assembly and test operations are due to begin later this year, according to Malaysian Prime Minister Anwar Ibrahim, following an earlier briefing with Tan. Intel has also outsourced EMIB production to Amkor's Songdo facility in South Korea, and its next-generation EMIB-T packaging rolls out across production fabs this year.

With Magdeburg and the Penang delay having stripped packaging options elsewhere, Rio Rancho is now the load-bearing U.S. node for the back-end work that makes Intel's entire chip roadmap possible.

Two deadlines and three things to watch

Intel’s 14A commitment window and the cutoff for tax credits both converge in the second half of this year. Tan’s stated expectation is that customers make firm supplier decisions between the second half of 2026 and the first half of 2027, with results from the upcoming October PDK potentially being the trigger for those decisions.

On June 8th, Cadence announced a multi-year agreement with Intel Foundry to co-optimize designs for 14A and deliver production-ready process design kits. This is exactly the EDA groundwork that needs to be in place before any fabless customer can commit volume, and a committed volume customer will be what unlocks acceleration at Ohio and gives Fab 62 a job. The alternative, per Intel, is to cancel 14A altogether.

Unlike the customer deadline set by Intel, the tax deadline can’t slip. The so-called One Big Beautiful Bill Act raised the Section 48D advanced manufacturing investment credit from 25% to 35% in July last year, but the law's termination clause is unchanged: the credit doesn't apply to “property the construction of which begins after December 31, 2026.”

Treasury rules let a physical-work test or a 5% spend safe harbor establish a construction start, so Intel has roughly six months to break ground on any new shells, in Ohio, Arizona, or Oregon, that it wants the U.S. government to part-fund. The government, of course, has been a shareholder since August, when $5.7 billion in unpaid CHIPS grants from Intel's $7.86 billion award and $3.2 billion in Secure Enclave funds were converted into a 9.9% equity stake.

Ultimately, we’re going to be watching for three things before January: a named 14A customer with a volume commitment; a construction-start announcement timed to beat the credit deadline; and 18A yield milestones that free up the Arizona capacity Intel’s currently sitting on.

We learned a lot about Intel’s upcoming plans for desktop CPUs at Computex 2026. In classic Intel fashion, we’ve already heard a lot about the company’s next-gen CPUs, codenamed Nova Lake, even while the recent Arrow Lake Refresh CPUs are still warm from the oven. But on the ground in Taipei, we heard not only more about Nova Lake and the Z990 platform it’s arriving on, but also how Intel intends to handle the rollout and how it will fill the gaps in its lineup with “Raptor Lake Next,” which is supposedly slated to launch next year.

Trade shows are the best opportunity to learn details about unreleased products before they show up in a press deck, and simultaneously the worst venue to do so. With jet-lagged representatives and reporters, thousands of people whizzing past, and the threat of Jensen Huang showing up to sign components and shut down a floor on a moment’s notice, it’s easy for things to get lost in the shuffle. So, we’re going to work through everything we learned about Intel’s upcoming plans in stages, starting with details that are confirmed, and working toward more speculative murmurs.

Intel has a fairly aggressive consumer roadmap, which the company itself would tell you – and the company told us as much at Computex, as a matter of fact. Both Nish Neelalojanan, senior director of client product management, and the recently joined Alex Katouzian, executive VP and GM of client, played up Intel’s roadmap to Tom’s Hardware, and for good reason.

Chronologically, Intel’s plans look something like this: We’ll see the first Nova Lake SKUs roll out at CES 2027. A few months later, we’ll see a refresh on the LGA 1700 socket with “Raptor Lake Next” CPUs, and come Computex next year, Intel will launch a 52-core flagship Nova Lake SKU. None of that is confirmed by Intel, and we have varying degrees of confidence in each step of the roadmap, so take it as speculation for now. We’ll dig more into the details we have and what’s simply rumored below.

What about AMD?

Before Intel, we should at least look at why we’re not talking about AMD’s next-gen desktop plans. Basically, we don’t have a ton of information on Zen 6 CPUs yet, and even less information about Olympic Ridge, the desktop consumer lineup of Zen 6 chips. Computex didn’t change that fact.

At Computex, AMD revealed the Ryzen 7 7700X3D, relaunched the Ryzen 7 5800X3D, and brought the RX 9070 GRE to the rest of the world. Unlike previous years, AMD didn’t hold a keynote, where we might’ve seen a more concrete tease of Olympic Ridge; AMD has already teased Zen 6 broadly several times. Bigger Zen 6 news is likely at the company’s Advancing AI event next month.

Although AMD hasn’t said when Olympic Ridge will launch, we originally expected it in late 2026. Now, 2027 is very likely. AMD has shifted the Zen 6 conversation toward its EPYC Venice chips, and confirmed production ramp on Venice in May. Although AMD traditionally leads with a consumer launch at the turn of a new microarchitecture, it’s unlikely that Olympic Ridge will launch before Venice. Demand for CPUs is spiking in the data center for agentic AI workloads, after all, and AMD is adjusting accordingly.

Olympic Ridge probably isn’t top of mind right now, from both AMD itself and its partners. AMD laid the groundwork for a unified CPU architecture generations back, and Intel’s approach has been a bit more disparate across client and data center (although that’s been changing with releases like Xeon 6 and Xeon 6+). We don’t know when Olympic Ridge news will arrive, but it almost certainly follows far greater detail about Zen 6 in the context of Venice.

What’s confirmed

Let’s start with the concrete details about Intel’s future CPU plans. These are things we have direct evidence for, be it photos, our own hands-on time, or sources we’re extremely confident in. At least two Z990 motherboards were at Computex, a third is rumored, and we saw (and held) what looked to be a near-production model in a closed-door meeting. And from that, we can already tell a lot about Nova Lake.

First, the LGA 1954 socket, which has now been pictured (we were told not to take pictures, but someone else did the dirty work, it seems). It’s the same size as the LGA 1851 socket, measuring 45 mm x 37.5 mm, and it retains compatibility with existing coolers, which we were able to confirm at Computex. It features more pins, as the name reveals, and uses the 2L-ILM, or two-lever Independent Loading Mechanism. The picture of the socket circulating matches what we saw at Computex.

The motherboard we saw featured dual 8-pin EPS connectors, along with an 8-pin PCIe connector near the bottom of the board, which is said to provide auxiliary power to the CPU. We’ve seen a leaked photo of the Z990 PCH now, which is said to draw more power due to broader PCIe 5.0 support. The Z990 board we saw, at least, had three PCIe 5.0 M.2 slots, along with three PCIe 5.0 expansion slots. Short of perhaps specialized designs with extra M.2 slots, we expect Z990 to support PCIe 5.0 across the board.

As for the chips themselves, all that is confirmed from Z990 motherboards is that Nova Lake can scale up to a high-end power design. We’ll speculate more on specific numbers later, but we’ve seen auxiliary power beyond two 8-pin EPS connectors on two Z990 motherboards now, and the motherboard we held had an extremely high-end VRM design; we can’t say more than that at this point.

An important caveat here is that we’re dealing with high-end motherboards and discussing how high the platform can scale, not how it will scale. Plenty of ink has been spilled about Nova Lake’s supposedly high power draw, but we really don’t have details about the chips themselves, rather just the tippy-top of the platform that will support them.

Outside of Z990 boards, Intel has confirmed that Nova Lake is “coming at the end of 2026.” That’s what CEO Lip-Bu Tan said at the company’s full-year 2025 earnings call back in January. What we were told by multiple vendors at Computex is Q1 2027, with a portion of those vendors specifically pointing to CES 2027. Similarly, with Z990 motherboards, some vendors said Q1 2027 while others said Q4 2026 (one even hinted at Q3). Believe it or not, these timelines actually all match up.

What’s lost in translation here is when the sale is happening. Before Nova Lake launches publicly, Intel and motherboard vendors will need to sell products into the channel, which, a few months later, will be available for sale at retailers for you to buy. What we’re likely looking at is sales into the channel in Q4, a public launch of Nova Lake at CES 2027, and retail sales in Q1. When Tan says Nova Lake is coming at the end of 2026 to a group of investors, he’s likely referring to selling into the channel, not the final retail sale.

What’s likely

Now, we’re getting into a bit more speculation. These are some of the details we heard about at Computex, or confirmations of previous rumors that we don’t have any concrete evidence for. Given the conversations we had at Computex, and a healthy dose of critical thinking, these are the details that are likely but not confirmed. There’s always a chance we’re just blind men touching an elephant on some of these points.

First, Nova Lake. For nearly a year now, it’s been rumored that the highest-end Nova Lake SKU will scale up to 52 cores. That’s the number we heard at Computex, as well, but not as a typical flagship. Rather, we heard that Intel plans to lead Nova Lake with a 28-core flagship, which will launch at CES 2027, and introduce a high-end 52-core model later in the year. The timeframe we heard was Computex 2027, but if anything is subject to change, it’s a release date that’s a year away. For now, let’s call it later in 2027.

The 52-core SKU will apparently come with 16 Coyote Cove P-cores, 32 Arctic Wolf E-cores, and a cluster of 4 LP-E cores; we didn’t hear that at Computex, nor anything to the contrary, but that’s what has been previously rumored. That model will reportedly come with two compute tiles, so the 28-core model with a single compute tile will likely look like an 8 + 16 + 4 split. That’s pure extrapolation at this point, however.

As for the 52-core model, we were told it comes with a PL1 of 175W and a PL4 of up to 700W. The PL1 number is what’s important here. Although that is a sizable increase over the 125W PL1 of both the 285K and 14900K, 52-core Nova Lake doesn’t sound like a direct replacement for those parts. Given the timing and extra power demands, it looks more like a spiritual successor to Intel Extreme Edition chips, targeting enthusiasts with deep pockets and the HEDT crowd.

Nova Lake is treaded ground at this point, however. Something new we learned about from Computex is “Raptor Lake Next.” After hearing the name, we asked Intel, which declined to comment on Raptor Lake Next at this time. Apparently, however, it will be the third refresh of Raptor Lake CPUs on the LGA 1700 socket, particularly targeting budget-conscious builders while Nova Lake satiates the enthusiast crowd.

There are some pieces of circumstantial evidence that point to a reintroduction of LGA 1700 CPUs. First, this has been previously rumored. In April, prolific leaker Jaykihn hinted at another Raptor Lake refresh coming in 2027. We’ve now heard that the range is called Raptor Lake Next from multiple sources, and it’s specifically coming in the first half of 2027, some months after the initial Nova Lake launch.

Additionally, multiple motherboard vendors told us that they’re ramping production of LGA 1700 motherboards, including DDR4 boards, though they didn’t say it was in relation to any new CPU releases. Intel itself has dropped a few hints, as well. Earlier in the year, Intel’s Robert Hallock said that Raptor Lake will be “abundantly available” in the market, and at Computex, Intel’s Nish Neelalojanan told Tom’s Hardware that Intel “will continue to make sure that there are products which can take care of older memory technologies.”

It would certainly make sense for Intel to refresh Raptor Lake a third time. Although data center demand is offsetting it, the decline in desktop sales from high memory prices hits Intel and AMD on the balance sheet as well. Just about everyone we spoke with at Computex talked about the state of memory prices, and Intel has a DDR4 platform that it’s still actively selling on the market. AMD, with a hard switch to DDR5 with Zen 4, has to reach back further to revitalize DDR4 options, but Intel already has a small ecosystem of DDR4 motherboards and CPUs available now, which it could easily bolster. We’ve heard that bolster is coming in the opening months of next year.

What that range looks like remains a mystery, however. It could be a proper refresh, or it could simply be an infusion of 14th-gen stock (and LGA 1700 motherboards) into the market along with new price points; both Raptor Lake generations have slowly crept up in price since the end of last year. The important thing here is that it seems Intel is targeting LGA 1700 for the lower end of the market, as Arrow Lake, with its underperformance and high price due to exclusively using DDR5, won’t provide the last-gen value bridge that previous generations have.

After Tom's Hardware originally broke the news about Raptor Lake Next, we followed up with Jaykihn, who provided a few specs.

*Naming unconfirmed by Intel, specifications rumored

The specs we've heard about are for the four SKUs above, which would comprise the main lineup of chips with integrated graphics enabled; apparently, Raptor Lake Next will include options with the iGPU disabled, as well as mobile chips. The final branding is unconfirmed, but we've heard that Intel intends to launch under the Core Ultra 200 name.

Out of the four SKUs, the 16-core Core 5 looks like Intel's breadwinner. Throughout 12th- to 14th-Gen, Intel topped out Core i5 models at 6 P-cores. You'd have to step up to a Core i7 for 8 P-cores. If these specs are correct, Intel is stepping down to an 8 P-core configuration a tier in branding, which will hopefully come with a cut to price.

What’s still up in the air

Some of the finer details of Nova Lake are still up in the air. That is, we don’t have any direct evidence for them, nor any corroboration from Computex. That’s not to say that the details here are false. Rather, we just need more information to say, for sure, that some of these details are a part of the Nova Lake lineup.

First and most obvious is bLLC, or big Last Level Cache. This is one of the earliest Nova Lake rumors that is still circulating, and for good reason. Intel hasn’t found an effective counter to AMD’s 3D V-Cache CPUs in more than four years. We’re closing in on half a decade where AMD has entirely owned the high-end of PC gaming, which has continually eaten away at Intel’s market share. bLCC is, apparently, Intel’s counter to 3D V-Cache, using its own Foveros 3D hybrid bonding to stack additional last-level cache.

Tom’s Hardware asked Intel CEO Lip-Bu Tan and a panel of executives at the company how it plans to address X3D CPUs, and Alex Katouzian, a 20-year Qualcomm veteran who recently joined Intel in a leadership role over the client group, said the following: “When I first came in and started reviewing road maps for the team, I was very pleasantly surprised. So, stay tuned, a very strong roadmap [is] coming, and we will be gunning for that section of the market as well. And so, please stay tuned.”

Context is important, but Katouzian is really only saying that Intel is gunning for high-end gamers with its roadmap, which, of course, it is. Otherwise, bLLC has entirely been a topic of the rumor mill. Intel has indirectly teased it with PR hits about its packaging capabilities, but that extends far beyond bLLC. Hybrid bonding, especially from a foundry perspective, has far greater legs in the data center.

Although Intel has the packaging and bonding capabilities, the scale of them for a mass-market product like Nova Lake is questionable. Intel would need to bond the SRAM to the logic tile with Forveros and package the chip with EMIB, creating the “EMIB 3.5D” combination that Intel has talked about previously. We first saw EMIB 3.5D on the Ponte Vecchio data center GPU, but most recently and relevantly on Clearwater Forest, Intel’s first foray into putting 18A in the data center. The capability is there, but if Intel can scale that up to a consumer range with more limited die space and higher per-core performance remains to be seen.

One advantage of Intel’s hybrid bonding and advanced packaging is that it can package dies from other foundries, not just those from Intel foundries. That brings us to the second finer point about Nova Lake, which is the node. Originally, the assumption was that Intel would use 18A for Nova Lake. We have 18A on mobile with Panther Lake, in the data center with Xeon 6+, but not on the desktop. Further, Intel has previously commented about reshoring its manufacturing for consumer chips after a brief stint with TSMC for logic tiles in both Lunar Lake and Arrow Lake.

Around this point last year, however, rumors started circulating that Intel is using TSMC’s N2 for Nova Lake. The source of the rumor is flimsy, however. Well-known reporter Charlie Demerjian of SemiAccurate reported in July 2025 that Intel taped out a major product. The report didn’t mention what product, what foundry, or even include “TSMC” anywhere on the page. Still, other outlets took the story, claiming that not only was Demerjian talking about Nova Lake, but also that he was talking about TSMC N2.

There are reasons Intel could use TSMC for the logic die. The company has reiterated that it’s shifting wafer capacity toward the data center, so if TSMC can fill additional capacity on the desktop, we could see TSMC on the main logic die. It’s also possible that TSMC is manufacturing other tiles on Nova Lake. Intel has consistently blended nodes in recent generations, so even if Intel were to confirm that it’s tapping TSMC for Nova Lake, that doesn’t necessarily mean the Taiwanese giant is manufacturing logic.

And, just as easily, Intel could absolutely be using TSMC for logic. That’s the point here; we really don’t know at this point, outside of vague reporting, getting swept up in the rumor mill, and taking on a life of its own. The Cinderella story for Intel would be Nova Lake on 18A, but given the struggles on 18A yields, it wouldn’t be surprising to see TSMC at the helm for Nova Lake once again.

Hurry up and wait

Intel needs a much more aggressive roadmap on the desktop than AMD, frankly, and that roadmap is starting to take shape. Although AMD and Intel compete on the finer points of performance, Team Red has almost exclusively taken market share away from Intel, quarter over quarter, for the past decade. There are only a handful of quarters in that time when AMD has lost market share, which it has always rebounded from in the quarter that follows.

Even if Intel still represents the majority of the desktop market — and it does based on the latest market research — the trend is abundantly clear. Add on top of that clear fumbles like Arrow Lake, and it’s obvious that AMD doesn’t need to move the needle much to continue swiping customers. Intel needs to make big moves to recover.

We should have more official details about those plans soon. Intel mostly sat Computex out on the consumer front, short of the Arc G3 range that, although exciting for gaming handhelds, is destined to be a niche product given the high prices of the devices those chips are going in.

For the past four years, Intel has held its Tech Tour event in the fall, taking the place of its previous Architecture Day, which took place in the late summer (most of those details have shifted to the Hot Chips conference in August). Intel has already told us that Hot Chips will have more details about Diamond Rapids, Intel’s next-gen P-core Xeons. That leaves Tech Tour for when we’ll likely get a full architectural deep dive on Nova Lake. Intel has yet to confirm Tech Tour 2026, but we have no reason to believe the company will sit out the rest of the year at this point. It also lines up with what we’re hearing about Nova Lake’s release — architectural details in the fall, a launch at CES 2027, and availability in Q1.

Regardless of when the exact dates fall, Computex made it clear that Intel is readying Nova Lake for a release soon. Multiple motherboard vendors brought Z990 motherboards to Computex and actively showed them to the press; I can’t imagine that was sanctioned by Intel.

As for Raptor Lake Next, Computex is the first quasi-confirmation we’ve heard of the range. That name apparently appears on Intel’s roadmap at some point in the first half of next year. With Nova Lake at the high-end and Raptor Lake Next in the midrange, Intel might have a one-two punch strategy to earn back some spots in the market, especially as AMD turns its Zen 6 focus toward the data center and prioritizes older architectures on desktop, given high DDR5 prices. Now, we just need to wait and see how those internal plans materialize as the rest of the year goes on.

We managed to grab pics of the newest upcoming server sockets from both AMD and Intel at Computex 2026. Both AMD and Intel are preparing to launch their next-generation server platforms that use all-new sockets, which enable new levels of performance, functionality, and power delivery.

AMD is a bit ahead with its SP7 platform in 2026, while Intel’s gargantuan 9324-pin socket will be used for Xeon ‘Diamond Rapids’ in 2027. While the platforms are entirely different, what makes them similar is the massive dimensions of CPU sockets and coolers.

AMD’s SP7 is the company’s next-generation socket that will support AMD’s 6^th Generation EPYC ‘Venice’ processors with up to 256 cores. The socket is huge and is rumored to support 16 DDR6 memory channels using 12.8 GT/s MRDIMMs as well as up to 96 PCIe 6.0 lanes (with the CXL protocol on top, though this is a processor, not a socket feature).

Based on information from Auras, the SP7 socket will be able to handle CPUs with a peak power consumption of up to 1,400W, so Auras and other companies are prepping liquid cooling solutions for these parts. In person, the socket is strikingly large, occupying most of my palm and overshadowing today’s server CPU packages.

Given the fact that the socket must support so many memory channels and PCIe lanes, it is not surprising that it is that large. Despite its enormous dimensions, the socket is still compact enough to enable dual-socket server designs, so AMD’s partners will be able to offer systems with up to 512 x86 cores as soon as its next-generation EPYC processors arrive later this year.

Meanwhile, for those systems that do not need so many cores and memory channels, AMD is prepping the SP8 platform that is set to offer fewer cores and DDR5 channels. Interestingly, Auras is working on water blocks for SP8 sockets as well, which means that the platform will still be quite mighty in terms of power consumption.

But while AMD’s SP7 is huge, Intel’s 9324-pin socket easily dwarfs it, as it is noticeably longer than the palm of my hand. The socket will work with Intel’s Xeon ‘Diamond Rapids’ processors with up to 192 cores, a 16-channel DDR5 memory subsystem supporting MRDIMMs, and PCIe Gen6 lanes.

Intel is yet to announce the processor base power of Diamond Rapids processors, though, since Auras is prepping water blocks for these CPUs, we're talking about circa 300W – 500W PBP and over 1 kW peak power consumption. Meanwhile, given that the socket is so massive, we would not be surprised if Intel’s 9324-pin socket will also support the Coral Rapids processors, presumably due in 2028 – 2029.

A Reddit user has demonstrated that SteamOS, Valve's Arch-based gaming operating system built around AMD silicon, can boot and run on an Intel Arc B580 discrete graphics card. Posting in the r/SteamOS subreddit as SaperPL, they documented the feat this week, pairing the Arc B580 with a Ryzen 5 5600 processor and getting Valve's full gaming-mode interface running on the card. The catch is that reaching that point took a Radeon card, a workaround for a broken installer, and a motherboard setting that nearly sank performance along the way.

The opening exists because recent SteamOS beta builds quietly widened hardware coverage. Valve's changelog for the beta cites improved compatibility with recent Intel and AMD platforms, language clearly aimed at the wave of Intel-powered handhelds rather than desktop Arc cards. However, because the underlying Linux graphics driver is shared, the same Mesa stack that targets Intel handheld chips also recognizes a desktop Arc GPU. SaperPL's system reported the card as Mesa Intel Arc B580 Graphics (BMG G21) on Mesa 26.1.2, running SteamOS 3.9.

Getting there was not exactly plug-and-play. According to the post, newer SteamOS images that supposedly already include Intel Arc support failed during setup. These images did not boot into the older live desktop-style installer with install, update, and recovery options. Instead, they started installing directly to the drive, then failed when the system tried to connect to the network and pull its first update. SaperPL says the same problem occurred even when testing with a Radeon RX 9060 XT, suggesting the issue was not limited to the Arc B580 itself.

The workaround was suitably PC-gaming messy. SaperPL installed an older “repair-main” SteamOS build using the Radeon card, pulled the required updates, and then swapped in the Intel Arc B580. After that, SteamOS booted on the Intel GPU and ran from the Main channel. The poster also noted that users without a spare Radeon card may be able to follow a Steam Community workaround to bypass the installer’s update failure directly, although that still leaves the process firmly in enthusiast territory.

The first performance results were mixed. SaperPL tested 14 games, including Cyberpunk 2077, Helldivers 2, Marvel’s Spider-Man: Miles Morales, Indiana Jones and the Great Circle, Toxic Commando, Hades, Rocket League, and others shown in the SteamOS library screenshot. The interface itself appeared to behave well, with the poster saying the Steam library and store navigation worked smoothly, even while downloads continued in the background. Gamescope also reportedly worked similarly to Radeon, apart from a VRR bug on FreeSync displays with HDR that caused occasional flickering.

Frame rates were another story. Indiana Jones and Toxic Commando were initially barely above 20 FPS at 1080p on the lowest settings, while Helldivers 2, Cyberpunk 2077, and Spider-Man: Miles Morales fell far below comparable Windows benchmark videos. The poster’s monitoring suggested the CPU was not the main problem, with the GPU often sitting around 80% to 90% usage while the Ryzen 5 5600 hovered between roughly 30% and 50%.

The biggest culprit turned out to be a familiar one for Intel Arc users: Resizable BAR. SaperPL later updated the post to say that ReBAR had been disabled on the Asus B450 Strix motherboard after a CPU change. Once enabled, Cyberpunk 2077 and Spider-Man appeared to perform as expected, while Indiana Jones and Toxic Commando improved significantly, though still not fully matching Windows reference results.

That detail matters because Intel Arc GPUs are unusually sensitive to Resizable BAR. Without it, the CPU cannot efficiently access the GPU’s full memory space, which can lead to severe performance drops. In this case, it made the difference between “SteamOS on Arc is broken” and “SteamOS on Arc is early, but actually running.” Even on Windows, leaving ReBAR off will severely impact Arc performance.

Commenters also pointed to another likely limitation: kernel support. Intel’s Arc drivers on Linux have improved considerably, but the newest performance work often depends on recent kernel and Mesa versions. If SteamOS’ Main channel is still behind the very latest Linux graphics stack, Arc performance may remain below what the same card can do under Windows or faster-moving Linux distributions.

For now, this is more proof of concept than a consumer-ready feature. Valve has not turned SteamOS into a general desktop gaming OS with clean support for every GPU, and the install path shown here is still too awkward for normal users. But the result is interesting. SteamOS running on an Intel Arc B580 suggests Valve's hardware net is widening, whether intentionally for desktop GPUs or indirectly through work on Intel-powered handhelds.

That could matter for future SteamOS machines. AMD remains the obvious fit for Valve’s gaming hardware today, but Intel has been pushing harder on Linux graphics support, and low-profile Arc cards could become attractive for small living-room builds if the driver stack matures.

Yesterday, we broke news of a third Raptor Lake refresh in the works from Intel, dubbed "Raptor Lake Next." Following that, new leaks have emerged from reliable tipster Jaykihn confirming the codename and detailing the upcoming family. Raptor Lake Next is slated for early 2027 and will land on the LGA 1700 socket as reported previously, but some outlets say it will also retain the existing Core 200 branding.

According to the rumors, Raptor Lake Next doesn't use Bartlett Lake silicon, which is Intel's special lineup for edge and embedded devices with only P-cores. That means a 12 P-core SKU has been ruled out for now, and that Raptor Lake Next will stick to the usual hybrid config. It's expected to scale across mobile and desktop with up to 125W parts and HX models as well, but it won't bring any new notable features.

Essentially, we're looking at rebranded 14th Gen CPUs that are likely being re-released because of their high yields. Intel spent a considerable amount of time and effort fixing the stability issues with 13th and 14th Gen families, so it makes sense the company wants to maximize its returns here. The Core-i9 14900K is still the most performant gaming CPU Intel has ever released, so calling this leftover silicon doesn't feel right either.

Jaykihn also provided further specs for the Raptor Lake Next, claiming it will only spread across Core 3, Core 5, and Core 7; no Core 9 SKUs in sight at the moment. At the top sits a Core 7 part with 8 P-cores and 12 E-cores, totaling out to 20 cores rated at 65W, same as the Core i7-14700. Then there's a 16-core 125W processor, which is identical to the Core i7-13700K, but it's counted as "Core 5" for Raptor Lake Next.

There's a special 10-core 65W part with 24MB of L3 cache because the previous 10-core silicon only had 20MB. It looks like the cache from disabled core clusters will still be accessible in certain Raptor Lake Next SKUs, and this might become a trend going forward. Lastly, we have a Core 3 CPU with 4 P-cores and no E-cores, running at 65W as well. Since all these chips are based on Raptor Lake silicon, they use Raptor Cove P-cores and Gracemont E-cores.

Keep in mind that RTL and RTL-R both came with Intel HD 700 series integrated graphics; the new Arc Xe architecture debuted with Arrow Lake on desktop. Nonetheless, Raptor Lake Next will work with DDR4 memory because it uses the LGA 1700 platform. That could help alleviate at least some of the burden of building a PC today as DDR5 RAM doesn't seem to be getting cheaper anytime soon.

Raptor Lake Next is apparently going into production in January 2027 so it could be available in Q1 2027, coexisting with Nova Lake as perhaps the value-focused option from the Blue Team. All rumors point toward Nova Lake being delayed to next year, but officially we still expect an announcement later this year. Regardless, the two families sure look like they'll overlap, which is why the Core 200 vs Core 400 distinction would be important for consumers.

Google has placed an order for Intel to build more than 3 million of its TPUs in 2028 after months of testing Intel's advanced packaging, according to The Information, citing four people familiar with the matter. They claim that Nvidia is evaluating Intel to build a future processor that fuses four GPU dies into one unit, tied to its Feynman architecture due in 2028, and that SK hynix is testing whether its high-bandwidth memory works reliably with Intel's packaging.

Specifically, SK hynix needs to know whether Intel can run packaging to the standard that AI accelerators demand. TSMC’s CoWoS is the industry-standard process for it and has been oversubscribed for more than two years. Intel’s embedded multi-die interconnect bridge, or EMIB, is the only alternative AI chip makers can realistically qualify at volume before the end of the decade.

This isn’t a first for Intel: Google and Amazon were reported to be in active discussions for their custom AI processors back in April, but the remarks from these sources move those “discussions” to a solid unit figure and production timeline, adding in SK hynix qualification that would ultimately determine whether any of it reaches Nvidia accelerators.

CoWoS bottlenecked

TSMC's leading-edge wafer lines and its CoWoS packaging are both at capacity. At the company's annual shareholders' meeting in Hsinchu on June 4th, CEO C.C. Wei said, "It will be a long time before we can meet customer demand," telling shareholders that the company simply can’t satisfy American customer demand for years, even as it builds out U.S. capacity. He had already told the Semiconductor Industry Association last November that TSMC's advanced-node capacity falls "about three times short" of demand.

The queue for CoWoS is concentrated across a handful of buyers. Nvidia is naturally expected to account for the majority of global CoWoS demand — about 60% this year — with Broadcom and AMD absorbing another 26% between them, leaving custom-ASIC designers and smaller AI-chip makers waiting behind the largest GPU order book in the industry. But the industry can’t wait, and both these smaller players and hyperscalers alike with multimillion-unit roadmaps need to qualify a second packaging solution rather than wait for capacity that TSMC says will be short for years.

As for EMIB vs. CoWoS, they solve the same problem in opposite ways. CoWoS mounts every die on a large silicon interposer that all signals and power must cross, and the interposer scales with package size, so reticle-class designs waste silicon at the edges. EMIB, meanwhile, embeds small silicon bridges in the organic substrate only where two dies need to connect, with no interposer at all. Intel cites package utilization near 90% EMIB against roughly 60% for interposer-class packaging, because small bridges tile efficiently while large interposers don’t.

Bernstein analysts estimate EMIB packaging costs a few hundred dollars per chip against $900 to $1,000 for CoWoS on a Rubin-class processor, though the firm flags the fact that there’s a “lack of an external production track record” in that estimate. As always, there’s a trade-off: standard EMIB routes power around the bridge through the substrate in long, resistive paths. That might have been acceptable for Sapphire Rapids and Ponte Vecchio, but not for HBM4-class accelerators that draw more current.

EMIB-T closes that gap by adding through-silicon vias to the bridge die for vertical power delivery, and it’s set to enter production fab rollout this year. Intel has said EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 stacks and scales to a 120mm x 180mm package carrying more than 38 bridges and over 12 reticle-sized dies. Jaguar Shores, the successor to the canceled Falcon Shores accelerator, is the likely first product to use it.

Gated by SK?

Working with SK hynix could be a huge boon for Intel, with the qualification of its packaging by the South Korean memory giant potentially deciding whether it reaches flagship AI silicon or not. SK held a 57% share of HBM revenue in Q4 2025 per Counterpoint Research, and UBS expects it to take roughly 70% of the HBM4 supplied for Nvidia's Rubin platform this year.

HBM stacks are themselves a packaging problem: multiple memory dies bonded vertically through TSVs, then mounted next to a host processor with tight tolerances on power and thermal behavior. Validating those stacks on EMIB rather than a CoWoS interposer is the test of whether Intel can package memory to the standard Nvidia and Google require.

An official thumbs-up from SK, or an HBM-4-on-EMIB-T production result, would convert Intel’s packaging from “tested” to “trusted.” But, until (or if) that happens, the split between accelerator types will remain: ASIC designers running lower memory bandwidth, including Google and Meta, can adopt EMIB sooner, while bandwidth-bound GPUs stay on CoWoS longer.

Intel still needs to prove EMIB

No named external AI customer is in EMIB or Foveros volume production today. Intel runs EMIB in its own server CPUs, including the 18A Clearwater Forest part whose 17-tile package uses 12 bridges, but every specifically named outside engagement so far, including Google’s order, points at 2027 or 2028 products or remains an evaluation.

Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and in Q1 2026, the division posted $5.4 billion in revenue against a $2.4 billion operating loss, with external customers accounting for just $174 million of the total. CFO David Zinsner told the Morgan Stanley TMT conference in March that the foundry is close to closing deals worth "billions per year in terms of revenue" on advanced packaging alone, against a pipeline he had earlier measured in the hundreds of millions.

Another unknown is process yields: Intel uses 18A, its first node with gate-all-around transistors and backside power, for Panther Lake and Clearwater Forest, an internal proving ground before courting outside logic customers. However, Intel's most recent guidance is that yields are improving 7 to 8 percent each month, accelerated by enhanced cooperation with external partners.

Intel is broadening support for its Binary Optimization Tool, or iBOT, with seven new games. Across the newly-supported titles, Intel claims an average performance jump of 12%, and increases as high as 27%. To unlock support for the new games, you'll need the latest Intel Platform Performance Package. Then, you'll be able to select the games under the Advanced tab in the Intel Application Optimization GUI.

We originally saw iBOT roll out with Arrow Lake Refresh chips like the Core Ultra 7 270K Plus, but the feature works on Panther Lake chips, as well as Intel's latest HX mobile chips, Core Ultra 9 290HX Plus and Core Ultra 7 270HX Plus. Older Intel CPUs can't use iBOT due to hardware registers Intel must tap into for optimization. However, Intel says it plans on supporting the feature on future CPUs.

Intel initially rolled out iBOT with support for 12 games, which has now expanded to 19 titles. In our iBOT testing, we found that the feature offered an 8% average performance improvement, with the feature climbing as high as an 18% improvement in Shadow of the Tomb Raider.

Here are the games Intel added with the latest update:

• Metro Exodus Enhanced Edition
• The Callisto Protocol
• Homeworld 3
• Ori and the Will of the Wisps
• Little Nightmares III
• Warframe
• Hollow Knight: Silksong

Across the seven new games, Intel claims an average performance improvement of 12% with the Core Ultra 7 270K Plus. Intel tested at 1080p with High settings, and it used 32GB of DDR5-7200 memory and an Nvidia GeForce RTX 5090.

At the higher-end of the spectrum, Intel saw a 27% jump in Hollow Knight: Silksong and 16% improvement in Warframe. On the other end, Metro Exodus showed just a 2% uplift, while The Callisto Protocol jumped by 8%.

Intel's approach with iBOT might seem a bit scattershot, with 19 games now supported and no clear pattern between them. There are some popular and widely-played titles, such as Warframe and Cyberpunk 2077, but also less-demanding games like Silksong and older titles that don't see much play these games, like The Callisto Protocol. Even as the list expands, this strange mix is likely to stick around.

That's due to how iBOT works. It's essentially a translation layer, not dissimilar from Microsoft Prism. However, Intel isn't translating instructions from one ISA to another. Instead, it's optimizing x86 applications to ensure they're using the latest, most efficient instructions. Intel does this optimization with Hardware Profile-Guided Optimizations, or HWPGO, tapping into the silicon to see what's going on while code is executing. Once Intel has its optimizations, it packages them into a profile and ships.

Although iBOT is a unique feature, it's not universally applicable. Some games (and applications, as iBOT works outside of games) are already optimized enough that iBOT provides no benefit. We've also seen performance differences between chips, even between the Core Ultra 5 250K Plus and Core Ultra 7 270K Plus. It would be interesting to see how the feature works on more constrained chips, such as Panther Lake.

Probably the most important processor in PC history was introduced on this day 48 years ago. June 8, 1978, marked the birth of the x86 architecture with the arrival of the 16-bit Intel 8086 CPU. This lineage continues to the majority of PCs today, almost half a century later. Ironically, this chip and its x86 architecture, the result of 18 months of R&D, was meant only as a stopgap because Intel’s complex, clean-sheet 32-bit iAPX 432 project was delayed.

The Intel 8086 was designed by a team of four engineers and 12 layout people led by Stephen P. Morse. Reports indicate that the impetus behind this project was to provide a practical, timely alternative to upcoming 16-bit Motorola and Zilog CPU designs. The fabled 8086 processor was only meant as a stopgap, as Intel had bitten off a bit more than it could chew with the iAPX 432 project, begun a year prior. As a side note, the 432 finally shipped in 1981 and was deemed too expensive, too complex, and fatally too slow when it arrived.

The 8086, the founding CPU in the x86 lineage, was marketed as Intel’s first 16-bit processor. It benefited from a degree of backwards compatibility with prior Intel 8-bit designs like the 8008, 8080, and 8085. Notable advancements over its predecessors included microcode for multiply and divide assembly language instructions.

Looking closer at the hardware tech specs, the Intel 8086 had around 20,000 transistors (29,277 including ROM and PLA) and was manufactured using Intel’s HMOS (High performance MOS) manufacturing process, originally developed for manufacturing fast static RAM products. The resulting 40-pin chip measured 33mm², and the minimum feature size was 3.2μm. Over its lifetime, it was released in clock speeds ranging from 5 to 10 MHz.

While the Intel 8086 founded the x86 architecture, the subsequent 8088 design (1979) would become the beating heart of the first IBM PC (1981) and that particular storied lineage.

Direct 8086 successors like the 80286, 80386, and 80486 would spearhead the Wintel alliance and establish the PC compatible as the default choice for productivity, home computing, and computer gaming enthusiasts until being sidelined by the Pentium CPU (also x86) from the mid-90s onwards.

Intel released its Core i7-8086K 40th anniversary chip in 2018. What next?

To celebrate 40 years since the original 8086, Intel launched the Core i7-8086K 40^th anniversary chip in 2018. It looks like a pretty safe bet that we should get another tribute in 2028, marking the half-century anniversary. What will we get for the 50^th? Something that embodies the fun and enthusiastic side of PCs, we hope.

Also, it will be interesting to see if Arm processors begin to impinge upon the dominant x86 designs from the likes of Intel and AMD in the Windows PC market in the next couple of years. We’ve had Windows-on-Arm efforts from Qualcomm and Mediatek try to usurp x86 with muted success.

At the recent Computex 2026 there was a lot of buzz about Nvidia’s RTX Spark Superchip, a powerful new Arm platform designed to transform Windows 11 into an agentic AI operating system. Looking back two years from now, will Nvidia and its partners have started to turn the tide against x86?

Intel just launched its Core 300 series of mobile CPUs, also known as Wildcat Lake, for the budget segment a couple of months ago. But rumors for a next-gen refresh are already surfacing, with the latest one claiming that it will be a noticeable upgrade. Reliable tipster Jaykihn has just suggested that the Wildcat Lake refresh due next year will move to an 8-core config, up from the 6-cores that Wildcat Lake has right now.

The post you can expand above says "4+0+4," in reference to a rumored Wildcat Lake Refresh chip with 4 P-cores, 0 E-cores, and 4 LP-E cores, totaling out to 8 cores. Wildcat Lake today also has 4 LP-E cores but only 2 P-cores, so we're looking at a doubling in this aspect, and that should translate to real-world performance improvements. Keep in mind that these are Cougar Cove P-cores along with Darkmont-based LP-E cores, borrowed from Panther Lake silicon.

After all, Wildcat Lake is essentially just a cost-efficient and downsized version of Panther Lake that has an infused, monolithic CPU+GPU tile instead of separate chiplets bonded together — both are manufactured using Intel's 18A process. Wildcat Lake is, therefore, branded as the "Core 300" series, with the "Ultra" moniker removed to specify its lower-end capabilities.

Just two days ago, a leak from the same insider claimed that a 6-core Nova Lake mobile part was cancelled because that slot would be better filled by the Wildcat Lake refresh instead. Intel likely didn't want the two to overlap, and now that we know about a potential 8-core config, it makes even more sense. Jaykihn also replied, saying that Wildcat Lake refresh will still have 2 Xe3 cores for integrated graphics.

In the replies to the post attached above, Videocardz separately claims the Wildcat Lake refresh would be part of the Core 400 series, but only for the Core 5 and Core 7 SKUs. The lowest-end Core 3 SKUs would still be branded as the Core 300 series, as they will not be getting refreshed. This could mean Intel is trying to target a more upscale audience with its Wildcat Lake refresh, while the cheapest parts remain unchanged.

Intel has published specifications for the Xeon 6377P, a 12-core server processor that pairs enterprise-grade features with clock speeds more commonly associated with high-end desktop CPUs. According to Intel's product database, the chip, based on Bartlett Lake silicon, has a recommended price of $1,045 and is scheduled to launch in Q2 2026. The 6377P is also notable as the first P-core-only processor Intel has placed in its enterprise Xeon lineup.

The Xeon 6377P appears to be an unusual addition to Intel's server lineup. While modern Xeon processors typically emphasize high core counts, large memory capacities, and extensive I/O connectivity, the new chip instead prioritizes frequency, boosting up to 5.7 GHz while maintaining a relatively modest 95W TDP.

Based on the specifications, the chip looks quite different from what most buyers expect from an Xeon. Dual-channel memory, a 128 GB capacity ceiling, 20 PCIe 5.0 lanes, and single-socket-only support are all constraints that would be unremarkable on a workstation processor but stand out on a $1,045 server part.

Intel's Xeon 6 lineup normally spans the high-core-count Granite Rapids P-core parts and the 288-E-core Clearwater Forest and Sierra Forest parts. Dropping a 12-core Bartlett Lake die — basically a desktop CPU with ECC support and a server product code — into this family appears to be a deliberate choice to address single-socket, entry-level server deployments where raw core count matters less than per-core performance and platform familiarity.

One standout number is the 5.7 GHz maximum turbo — unusually high for server silicon, where power efficiency and core density typically dominate the conversation. The 95W TDP — genuinely low for a $1,045 server chip — makes that figure even more impressive.

Now, not every enterprise workload needs dozens of cores. Electronic design automation, CAD, software compilation, financial modeling, and certain industrial control workloads are often bottlenecked by single-threaded or lightly threaded performance. For those use cases, a 5.7 GHz Xeon with ECC memory, PCIe 5.0, platform validation, and guaranteed long-term availability is a more targeted fit than a 64-core EPYC with slower per-core clocks.

On the other hand, the competitive picture is less flattering. AMD's EPYC 4005 series, built on Zen 5, targets the same single-socket entry-level segment at lower price points and with a newer architecture. The earlier EPYC 4004 series topped out at 16 cores on AM5 — more cores than the 6377P at a lower RCP. Intel's counter-argument may be per-core performance and the existing LGA1700 platform ecosystem. However, the chip's AVX2-only instruction set, with no AVX-512 support, may give pause to workloads that can use wider vector operations — a notable omission at this price.

So, why would a buyer choose the 6377P over a Core i9 running on a high-end desktop board? The answer probably lies in what consumer platforms don't offer: certified ECC support, validated system configurations, and the multi-year product lifecycle commitments that enterprise procurement often requires.

Intel has not indicated whether the 6377P will be compatible with existing consumer LGA1700 motherboards, and given its Server/Enterprise use designation, OEM system availability is the more likely path to market.

Intel launched its Xeon 6+ "Clearwater Forest" processors at Computex 2026 in Taipei, and on Monday, two of the individuals responsible for the product sat down with the press to answer questions. Kira Boyko, Product Line Director for E-Core Xeon Products in Intel's Data Center Group, led the session, which was joined partway through by Tim Wilson, Vice President and General Manager of Intel's Data Center Silicon Engineering group.

Across roughly half an hour, the two addressed why Intel stripped hyper-threading out of its E-core server parts and the technical case for bringing it back, the agentic AI demand surge that has left expensive GPU fleets idling while they wait on CPUs, the deliberate decision to ship Clearwater Forest with only AVX2, and 18A supply so tight that allocating chips between customers is "daily, in some cases."

Diamond Rapids, Intel's next P-core Xeon, drew repeated questions, but Intel deferred any detail, with Evangelista pointing reporters to fuller commentary roughly two months out. That timing lines up with Hot Chips, where Intel is expected to share more on Diamond Rapids.

Clearwater Forest spec changes

Clearwater Forest tops out at 288 Darkmont E-cores per socket and 576MB of L3 cache, and is Intel's first data center CPU built on its 18A process.

Kira Boyko: It's our most performant Xeon on the market today, specifically for scale-out workloads, so it's not just a per-watt angle of fossil performance.

Jake Roach, Tom's Hardware: Was that the driving force behind the big spec changes compared to Sierra Forest? Obviously, it's double the core count, but I think there's over five times the amount of L3, and a huge increase in TDP.

Kira Boyko: The TDP is mostly that it is socket-compatible with the version of platform design that we had for Granite [Rapids]-AP before, and that is a higher-TDP product. Our initial E-core part was lower TDP, and this one has roughly the same range as the Granite version, so that's part of the platform-design alignment. But in general, we found that our customers were mostly targeting higher-TDP spaces anyway for the core density they were after, so it ended up working quite well. We already had a design that served those spaces.

Jake Roach: And the L3, was that another workload type?

Kira Boyko: You're right, a little over 5x increase, from the hundreds up to 576-ish [MB].

Jake Roach: If you have the flagship, that's quite a lot of L3.

Diamond Rapids and hyper-threading

On its recent earnings calls, Intel CEO Lip-Bu Tan has said that moving away from simultaneous multi-threading (SMT) "put us at a competitive disadvantage" and that the company will reintroduce it with the Coral Rapids generation, the P-core Xeon that follows Diamond Rapids. Intel's current shipping E-core Xeons, Sierra Forest and Clearwater Forest, run a single thread per core.

Jake Roach: I appreciate that we can't comment on future products, but there was a tease in the press deck for Diamond Rapids. It's a very anticipated product. I want to ask about hyper-threading. During the last two earnings calls, Lip-Bu Tan has referenced that hyper-threading will return with Coral Rapids. We don't currently have a Xeon P-core product without hyper-threading shipping. Does that mean Diamond Rapids does not have hyper-threading?

Andrew Evangelista: We'll comment more on Diamond Rapids [later].

Kira Boyko: I will say that E-core is single-threaded. It has the core density for the workloads it's servicing, and we are not expecting it to be replaced by Diamond Rapids. We're expecting the workloads that need more of the high-performance aspect of a P-core to go from Granite to Diamond, whereas the more scalar workloads for E-core will stick on Clearwater Forest, continue to be serviced through this next generation, and then pick up with the generation after that.

Andrew Evangelista: I think it was your question that prompted us to talk about Diamond Rapids in general. More to come.

Kira Boyko: The only thing I can really say from a Diamond perspective is AET, the new feature we're introducing on Clearwater Forest. That is expected to roll out across all of our Xeons going forward, so you can expect to see it on Diamond and future ones as well. What the roadmap looks like from a feature perspective gen to gen, I don't have any level of detail for today. But it is definitely being introduced in Clearwater. We have a number of customers deploying it on Clearwater, and others who are more classic P-core customers, with different workloads, running proof-of-concepts on Clearwater so they can hit the ground running with Diamond.

Jake Roach: I had to ask.

Kira Boyko: You're like, "That's not what I wanted, I wanted way more detail."

Jake Roach: There are a lot of articles that have been written saying it's confirmed Diamond does not have hyper-threading, and I haven't been able to find that confirmation anywhere.

Kira Boyko: There's a lot out there on Diamond that is all over the place. There are statements about [unclear] variants, and just a lot of rumors.

Andrew Evangelista: We'll have more official commentary to come, and that's what folks are anticipating. We understand there's excitement, and we'll share more [in two months].

Agentic AI and CPU demand

Journalist 2: What are customers telling you about this agentic AI wave, how they're dealing with it, and how Intel plays into that going forward?

Kira Boyko: Customers are just starting to understand their own AI deployment models, and a lot of them still aren't quite there yet. Many started by investing in GPUs and are now realizing they don't have the CPU counterparts to actually keep those GPUs going. So they made this huge investment, and they're running at something like 20% to 30%, something quite low. They're understanding that there's this space where certain workloads can be offloaded to more efficient CPUs, and that's exciting from a Xeon 6+ standpoint. Others are still going to be partnering with their providers, looking at industry white papers to understand how to best use their AI strategy.

Journalist 2: Just as an outside observer, it seemed like CPU demand was going, and then November and December happened, and everything got sold out instantly. What percent of current demand is agentic-AI-driven versus prior? I'm trying to get a sense of what it is now, and what it's going to be like six to nine months from now. It seems like a paradigm shift happened, and we're going to be riding this trend for several quarters at least.

Kira Boyko: I think we are. I think we're also going to see quite a bit of data center modernization and consolidation, looking at what workloads are already out there that can be consolidated onto CPUs. Some maybe are designed for agentic, maybe aren't, but are more storage-oriented, or workloads that can be serviced just fine on something that isn't super intense. So you can get a little more performance and energy back, and then use that to service some of their AI workloads as well.

Application Energy Telemetry

AET, or Application Energy Telemetry, is a Clearwater Forest feature that gives operators application-level visibility into energy use, which Intel says can be used both to tune workloads and to bill customers on measured rather than estimated consumption.

Jake Roach: You mentioned AET, and I know that's a really big thing with this launch. Is there any connective tissue with what we saw with Arrow Lake Refresh on the consumer front? AET is taking information from actual registers in the silicon. There's hardware on the chips doing it. Similarly, with iBot on Arrow Lake Refresh, it was hardware-enabled, where you could get these readouts running workloads and see where they could optimize. Is there any connective tissue there, or are these completely separate?

Kira Boyko: We can get back to you on whether there's some collaboration. Usually our teams are very separate, but it's very possible there is some, so we'll find out. My understanding is that this is highly customer-driven. Sometimes we leverage existing technologies.

Jake Roach: This is more to satiate my own curiosity.

Andrew Evangelista: Let me grab Tim for a second to answer that, because that's a silicon-engineering-level question. He's worked on both client and enterprise.

Jake Roach: Yeah, just because you're using Darkmont, there's at least a capability there.

Kira Boyko: Touché. Moving on to the next generation, which is not an E-core, it'll still be there as well. So even if there was some synergy, it would be moving forward to a different core base.

Andrew Evangelista: Circling back on two questions. One was similarities related to Arrow Lake.

Jake Roach: Basically, the hooks in Arrow Lake Refresh for iBot to optimize that translation. Are those hardware hooks something you're looking at? Is there any connective tissue there today?

Tim Wilson: I haven't looked at Arrow Lake in quite a while. To first order, I'd say fundamentally no, they're different use cases. Are we leveraging some of the same telemetry capability built into the hardware? It wouldn't surprise me.

SMT removal and its return

Intel split its Xeon 6 line into P-core parts with hyper-threading, such as Granite Rapids, and E-core parts without it, beginning with Sierra Forest.

Andrew Evangelista: The question on the decision for SMT and hyper-threading.

Journalist 2: Just why it was taken out, what the thinking behind that was. Was it a security thing?

Tim Wilson: I have a lot of my own personal thoughts. If you step back to the data center a couple of years ago, the thesis was that what matters is maximum core performance and then core density in the socket. So if I can deliver maximum core performance and increase the number of cores in the socket, do I really need [SMT]? One or two physical cores are always better than two virtual cores built on one physical core. I fully expect we will see use cases and workloads where that decision is incredibly useful and valuable and gives real-world value, and we've heard from some customers that, for what they're doing, single-threaded is the right answer. Having said that, there's a big portion of work that is still very much multi-threaded, especially in the virtualized space, so completely eliminating it is a problem, because we cut off some not-insignificant portion of workloads, especially when you're in a virtualized, licensed environment where licensing is based on cores and threads. So there was a technical reason for why you'd want [SMT], and that technical reason probably still holds. [...]

Journalist 2: Like a VMware thing, with a big price on cores. How are you going to market versus your main rivals, like AMD, and now Nvidia? What's the messaging going forward? From 18A to what's next, you'll be much better on the node side.

Tim Wilson: Our intention is to have leadership products with every generation, and we fully intend to do that going forward. Our go-to-market strategy is to sit down with customers and ask what they value, then go build leadership that meets those needs. With all our data center customers, we have deep discussions around the personality of the platform they want to build, beyond just cores and feeds and speeds. What is the system balance, the memory-to-compute ratio? How are they viewing multi-socket versus single-socket? What's the right number of cores for their workloads, for both private and public workloads, enterprise versus cloud? It's really sitting down in each of those and asking what the markets and customers buying our parts value, and how we optimize our products to meet their needs.

Journalist 2: Is that changing now with this agentic AI demand explosion? Are we going to see CPU racks with agentic AI as the primary use?

Tim Wilson: I'm sure you will, just like we've always built CPU racks. There are principles around CPU design that have always been true and will continue to be true. You want the highest-performance core you can build. Power efficiency is always going to matter as long as we're constrained by the amount of power you can bring inside a building's walls and the heat you can extract from them. Your memory-to-CPU harmonics, how much memory each workload takes, how much you allocate to each core, those are key. We've always designed for those parameters, and the end markets evolve over time.

Agentic AI is now exploding, but what's driving that explosion is not a new type of CPU. It's that the new AI workloads are not one call, one inference, one response. They're complex, execution-driven, multi-task queries that involve tens or hundreds of agents, and suddenly you need a control plane and an orchestrator, tasks the CPU is historically good at. How do I take a complex task and decompose it into subcomponents, figure out which can be parallelized and which depend on each other and need to be serialized, and pass those off to the GPU? I have to map memory to each of those subcomponents, and not all of them want the same memory, and I have to make calls to I/O, and in some cases to the OS or APIs.

Those are all things the control plane and orchestrator, the CPU, does really well. As you move away from a chatbot answer to "go do this analysis and give me a report on the actions I should take," that's a much different query, and the CPU plays a much bigger role. Data centers that have built on GPUs for the last three years are suddenly finding they're bottlenecked by the CPU. They have a massive GPU fleet that costs billions of dollars sitting idle, waiting for the CPU to respond. So do I see a future with agentic AI and CPU racks? Yes, but with characteristics very similar to the sorts of things we've always built into CPU racks. It's exploding because the things the CPU has always done well are the things in demand now.

Journalist 2: It seems like the whole storage infrastructure has to change, too.

Tim Wilson: That comes along with it. There's demand for storage, which drives I/O advancements and connectivity.

18A yield and wafer allocation

Clearwater Forest is a multi-process design: the compute tiles are built on Intel's 18A node, with base tiles on Intel 3 and I/O tiles on Intel 7.

Journalist 2: Questions you probably want to ask but won't answer. 18A yield volume for Xeon 6+, progressing?

Kira Boyko: We're ramping well. We have strong demand throughout the lifetime of the product, and we're working from a capacity standpoint across all of our products to hit customers at the point in time they need most. Compute is 18A, but we also have base on Intel 3 and I/O on Intel 7, so it's a multi-process product. We're mapping demand against all of our other products to figure out where we need to build.

Journalist 2: How do you choose who gets the product in this compute-supply-constrained world? Is it whoever orders first? You're sold out right now.

Tim Wilson: We give as many CPUs to as many people as we can. It tends to be more business decisions than engineering decisions, so it's a combination of long-term deals and customer relationships. The biggest problem is not demand in any way, shape, or form. The biggest problem is how we satisfy demand across every single product. If I have people demanding Xeon 6 and Xeon 6+, and still Xeon 5, how do I balance all of those and match where the supply constraints are in the industry? In some cases, customers are struggling with mismatches. They can get the GPU but not the memory to pair with it, or the memory but not the CPU. There's a lot of matching going on in the industry.

Journalist 2: On the client side, people are demanding even older products because they've already verified them.

Kira Boyko: I've seen that on the data center side, too. They've verified and tested a product, so they want that product. In such a supply-constrained environment, people will buy whatever’s on the table. And 6+ has the benefit of some backward-compatibility elements, the socket compatibility, and again, using processes that are hardened on previous products, so we can mix and match in some cases. We have customers looking for multiple products on multiple processes, and it's working with them to understand exactly what they critically need, when, and how we best service that across all their orders.

Jake Roach: If I'm remembering correctly, it was the earnings call before the most recent one, where we talked about wafer allocation split between client and data center, with a greater emphasis on wafers going toward the data center. Is that still the plan?

Tim Wilson: That's definitely the plan, and we're always having those conversations. That's more of a foundry conversation than a product conversation. [...] The whole ecosystem is sucking up all the wafers and memory, whether it's client, automotive, or any of the other industries. AI data center tends to take the supply because they're willing to pay the most, and the rest of the industries can't pay the price until supply balances out. We saw a similar effect during COVID, though that was supply-chain-driven rather than demand-driven. Those trade-offs, Gen 5 versus Gen 6 versus Gen 7, are a weekly conversation.

Kira Boyko: Daily, in some cases, on CPU allocations. [...] Given the dynamic space, our customers are modifying on a regular basis. Can we shift? What do they really need, and when? If you're asking long-term whether we'll stay in these constraints, we do see a space where things will lighten up. It's not in the immediate timeframe.

Journalist 2: Dave talked about multi-year hyperscaler contracts. What's the latest on that? Are deals getting signed, and are you getting more requests for those kinds of contracts?

Tim Wilson: I doubt either of us is the right person, by the way. They don't trust us with a lot of that information.

Journalist 2: You're not talking with data center customers on the purchase side?

Kira Boyko: We're not in the contract negotiation.

Tim Wilson: There's a principle here. If you mix commercial negotiations in with the technical discussions, it doesn't work out well, so you generally try to separate them. You let the finance people argue over pricing and contracts, and let the engineers figure out the best products to build together. When you're talking with product-side engineers, we don't have a lot of that information, and even if we did, we probably couldn't tell you.

Journalist 2: What percentage of Intel's data center revenue is hyperscaler?

Tim Wilson: You can go look at our earnings.

[Session ends]

Intel’s Arc G3 chips are gunning for the AMD-dominated, high-tier integrated graphics market that has become such an important enabler of the modern handheld PC gaming experience. But as high-memory prices push up the costs of even entry-level discrete GPUs, there could be much more of a place for powerful onboard graphics in the PC gaming landscape in the years to come.

We sat down with Intel’s Senior Director of Product Management, Nish Neelalojanan, in Taipei, Taiwan, at Computex 2026 to talk more about the G3’s development and how it fits into Intel’s lineup. Here, we're presenting the full transcript of our conversation.

This transcript has been lightly edited for clarity.

Jake Roach, Tom's Hardware: So what was the idea behind the G3, because you guys have tried before, right? I believe it was with MSI? And now you’re putting a bigger emphasis behind it with a whole new branding.

Nish Neelalojanan, Director of Product Management, Intel: It was a combination of two things. So first of all, we started trying already with Meteor Lake, and yes, we were experimenting. This was all standard off-the-shelf parts, and we learned a lot as we came into Lunar Lake. The power management for handheld needed to be more customized, so we started tweaking further, and as we got into Panther Lake, the architecture lent itself to lower power gaming. We moved the E-Cores onto the performance cluster, so you have E-Cores both on your efficiency island and your performance cluster, that means your E-Cores have access to L3 cache, so E-Cores are now performant enough to run games.

A lot of the time, in a low-power scenario, you are more GPU-bound than CPU-bound because the GPU is power starved, so if you can reduce the power on CPU and dump it on the GPU, you'll get much better performance. So, with that architecture change with Panther Lake, now is the perfect time. All the goodness we've learned, we can capitalize on it. We have a silicon architecture, we can lend itself to low power, and we have big enough graphics now…

Jake Roach: A really impressive iGPU.

Nish Neelalojanan: So, that is what had the impetus on, hey, what if we did a CPU line, which is graphics first, or leading with a very big graphics, but small enough CPU that doesn't grab enough power, but good enough to run all your handheld games. It's great for handheld gaming or non-PC form factor, running low-power gaming. So we wanted to start a line of products, which would be integrated graphics forward, with the right CPU.

Jake Roach: And these are wholly unique entries, right? If I remember correctly, there's no 14-core Panther Lake.

Nish Neelalojanan: These are completely unique chips. So they are based off the same die, but we've optimized it with, like I said, core count, so that taking two P-Cores off, because most of the games are going to run on the E-Cores on the performance cluster, you also cut down on different I/Os, so you don't need as many ports on a handheld as you would need on a laptop, right, so you cut down, so it's cutting down all the things you don't need.

Jake Roach: Really focusing it on that form factor.

Nish Neelalojanan: Yeah, that will be on the hardware, and then software-wise, we have a lot of other software optimization. So, now in order to have them pinned onto the E-Core, we have a BIOS control optimizer, so extra ways to have your thread director direct your game threads onto your E-Cores.

It's basically making sure we are directing the game threads onto the E-Core. [We also have the] ability to do power gating, so that we have features like endurance gaming, which we had on the laptops. Now, for handheld, we've added some features, so you can go with different presets. You can say, I want 60 frames per second, and then it will optimize your profile accordingly, or I want 30 frames per second. So you have a frame cap, and then your SOC resourcing is optimized, so that you will increase your battery life 2, 3, 4, hours.

Jake Roach: Battery life is so important for a handheld, right? I was playing a little Forza Horizon 6 on the plane coming over, and one way that I'm doing that right now on Linux is with Lossless Scaling, with frame generation in any game. As you're saying, apply that 30 fps cap frame generation to the mix, and you can get really good perceived performance.

Right now, you guys have multi-frame generation through XeSS 3 through specific games, but there's no driver. Is that something you're looking into, given how important that can be for the local gaming experience?

Nish Neelalojanan: So, 100 plus games have already enabled MFG, but you could imagine, as you said, it's important. So we're exploring, but as we get closer, we'll talk more about when and where it intercepts.

Jake Roach: The other thing I did want to ask about was form factors, which is something you kind of hinted at. Right now, with component prices being so high on just a typical DIY PC, we're seeing a really big push for budget laptops for people that maybe don't need as big of graphics and handhelds for people that really care about gaming as a laptop replacement. I'm just curious, kind of broadly, what you think about the dynamics between these form factors? Is this something that is just a temporary market connection, given that prices are so expensive, and are you planning around that, or is it something more long-term? Where do you think these are going to be the preferred form factors?

Nish Neelalojanan: I think, from a budget-conscious perspective of value buyers, our core 300 series, I think probably this is the first time in a long time the mainstream is getting some of the new ideas, right? So, today if you take a value-conscious segment in the past, it was always, hey, you have the big innovation, which we launched, it gets waterfall down. But as the innovation started getting expensive more and more, that waterfall did not happen, it was basically take the old chip, do some minor updates. So we wanted to take all these new like battery life performance uplifts, and you know, having the new AI updates, all of that, but to be able to be affordable, that's what is Wildcat Lake, or Core 300 series. So that's kind of for the budget-conscious buyer, we wanted to make sure we put some new IPs out there, because I don't think anyone is putting that out.

So that's part A. Part B of your question is handheld as a form factor. I think handheld as a form factor is interesting. Different people are trying to do multipurpose use, so would it ever go from companion to main? TBD. But can it expand its use cases from, hey, can I have a handheld, can I have a docked experience? I think long-term, yes. Currently, the software interfaces and a lot of the, let's say, ecosystem around it needs to evolve for it to be meaningful, but there's a lot of experimentation around dock experiences and stuff, which we are working with partners to experiment, but as it stands, I think handheld alone as it's gaming first.

A lot of our partners are experimenting; they're having all those capabilities available. How can you dock, how can you connect keyboard and mouse directly, and then be able to do it, because, like you said, costs are going up. If someone buys this, they want to be maximizing it.

Arrow Lake refresh's positioning

Jake Roach You touched on Wildcat Lake in the mobile segment, and recently we had Arrow Lake refresh, which was a really big readjustment in pricing. In particular, I'm just kind of curious to get more color on that, because when I reviewed those chips, I the expectations, I was briefed on them, and I was like, I know what to expect, but it was a very different Intel than I was used to working with on the desktop run.

Nish Neelalojanan: Short answer would be, we wanted to make sure we are putting out things which gamers would care about and show that we care about gamers, so this was an attempt or step one in getting to that expectation, right? And then obviously same thing with handhelds, making sure we are putting something which the gamers would want, so that's the highest level.

Jake Roach: I mean, again, seeing the results, we've essentially made the original Arrow Lake line outside of a few chips, irrelevant with these two chips. The 270K Plus scales above 285k and 250K can go toe to toe with either the Core Seven or Five.

Nish Neelalojanan: That’s a good thing, right?

Jake Roach: That is a good thing, but it's a good thing for us. It is not a good thing for Intel, right? Like, internally, that undermines your own product. And so I'm curious about the decision there, because at some point you had to have had pushback on, hey, this $300 Core 7 is going to undermine our $600 Core 9 flagship.

Nish Neelalojanan: It was just a decision made with end users in mind, and we want to make sure we are providing value as we come out, and if at all we need to start somewhere, right? And in terms of desktop, that was an effort to let's go with value focus first, and that will help us then gain confidence. From an enthusiast perspective, we needed to build back our reputation. I am sure you would agree with that, and this was, we’re making sure we are providing value to the gamers, and we start with Arrow Lake Refresh, and we have a very strong roadmap to come, so we want to continue.

Jake Roach: It did seem like an appetizer, almost, given you know everything that happened with Arrow Lake, and yeah, I appreciate you wearing that a little bit, because those were again, they were very interesting parts for a number of reasons.

Nish Neelalojanan: Savior [Kim, Intel Director of Client Communications] can correct me if I said something I shouldn't, but that was kind of highest level.

Leaving Hyper-threading behind

Jake Roach: Another question I had; This is more on the mobile side of things, or SoC side of things, is around hyper threading. So I have this question for the Xeon folks that I'm meeting with later today, because there have been comments in the financial reports, comments about returning hyper threading to the data center, whole lot of stuff around that on the consumer side of things. You guys left hyper threading behind with Arrow Lake. I'm wondering now that we have a desktop generation, a mobile generation under your belt. What do you see with that move to get rid of hyper-threading? And is there any consideration for maybe going back to some form of SMT in the future?

Nish Neelalojanan: Highest level, our decisions are always are we getting the right level of performance. The best way to achieve that performance is what we want to go with. Like you said before, with Arrow Lake Refresh, you're not only getting the right game performance at the right price point, but you're also getting almost 2x multi-threaded performance compared to competition, right? So, if you can deliver that without SMT, though the end user, it doesn't matter to the end user. In fact, you're actually getting even better multi-threaded performance because they're actual physical codes versus virtual threads, right? So that's where I would leave it at. We always reevaluate, but it's the best way to give that level of performance in that given price band or that given SKU. So we continue to keep re-evaluating, and different segments may need different things.

Jake Roach: Right now it sounds like it's working out well?

Nish Neelalojanan: Yeah, and like in terms of all the different agentic AI workloads, you need CPU as an orchestrator, having nth number of threads, cleaning up data, lining up a memory, a lot of threads help. So, like I said, when there is utility, and when there is a need, we will constantly evaluate it's, it's rigid to say, oh, it's behind us, or it's rigid to say, oh, we are going to run towards it: If it makes sense, it makes sense, yes. That’s where the data center decision is. They talk more about the growing workload, there is a need.

Jake Roach: It has been interesting. We're coming up at Tom's Hardware on 30 years, and we did a retrospective on CPUs, so I went back to the very first Pentium Two review on Tom's Hardware, and seeing the hyper-threading, and how it was used over decades, it was really fascinating to look at.

Nish Neelalojanan: A lot of the low-power segments, like now, handheld, yes? Those eight E-Cores on that performance cluster are significantly helping with all the low-power gaming, right? So, a lot of these decisions are paying off as it stands. As the workload evolves, as we evolve into different architectures, we will have to evaluate based on at that time what would be the right decision. Okay.

Jake Roach: For years now, Intel Foundry has laid out a really aggressive foundry roadmap. We saw 18A first and now we finally have 18A in data center with Xeon Six Plus. Is that the kind of the cadence we should expect going forward for Intel's cutting-edge hooks to see them debut first on the consumer front?

Nish Neelalojanan: It's the same answer I said before wherever it makes sense first. So we've got especially a lot of our consumer client CPUs, we pick the right process node, which made sense for the right tile, especially now we have multi-chip solution. It gives us the flexibility to pick and choose the right process node for cost, readiness, optimizing for R&D, because sometimes you won't have that IP on a different process, so it's easier to just reuse it, based on availability. Sometimes it's costing some bigger tiles, you can put it on latest and get it to get performance. Some of the tiles where you don't need to push frequency as much, you put it on an older node. And now with all the supply in and around the industry, picking the right process nodes, which is more available, is also going to be important. So we always go through all of these considerations and pick and choose, so there is no settling on client will start data center will follow, vice versa. It's we pick the right process choice based on that architecture, for that side.

Reacting to Nvidia's RTX Spark

Jake Roach: I want to get your reaction to [Nvidia’s RTX Spark]. If you need any better reminder that Twitter is not real life, there's a lot of talk on Twitter that Nvidia entering this market completely decimates and it rules everything. I don't think that's true, but I want to see your reaction to Nvidia getting into that space.

Nish Neelalojanan: I mean, Nvidia puts out great products, and they know how to do gaming. They know how to do all these different things. So we always take everything with a healthy dose of paranoia, but we are also very, very confident with our products, in the sense that X86… Let me put it this way, when we entered this discrete graphics business, our graphics business, it took a painful few years for us to work through all the drivers, all the compatibility issues, and everything ironed out, same thing goes on when an ARM CPU enters a market that's going to be tons of compatibility DRM issues, backward compatibility As a result, we are very confident that we have the right CPU, GPU mix for clients, both for gaming and when it comes to what you call AI inference workloads.

That said, Nvidia is a great partner. We will continue to work with them. You saw some of our announcements. We have some longer-term commitments with them, so both of us have different parts of the roadmap that we will expand together, where there'll be a roadmap where we will be partnering, and where there might be places where we will be competing, but I think it's great for the industry that there is different choices.

Jake Roach: I know, it's a weird situation, especially for Intel, because you guys, you guys do work with Nvidia. Yeah, when I pose similar questions to the other guys, they, they're a little bit more fiery in their responses.

Nish Neelalojanan: Compatibility is going to be a key thing there. x86 on the CPU side is going to have a lot of advantages. We talked about some of the new instruction sets, which got announced by the x86 Consortium, a lot of those lend itself as much to gaming as much as AI, and you'll see a lot of that being talked about more.

A lot of it were agentic AI examples and stuff, because you have to say AI three times before you can talk about anything else, but they also help with gaming significantly, so yeah, it doubles the amount of registers, which you would execute one instruction, so it's based off of AVX, but there’s a few others which came out with it.

The health of the consumer PC market

Jake Roach: Finally I want your reaction more broadly to the PC market right now, because we have all the rising component prices, we have very expensive laptops. On the desktop, it's really, really hard to build a PC right now. I think motherboard sales are down some 30-40% I know you're releasing products to address that market between Wildcat Lake and Arrow Lake pretty refresh, but I kind of want to see your reaction to how that pans out over the next maybe three to five years. Is it a continual area of focus, or is it something that hopefully we're just dealing with over the next few years, where we're really focusing on the budget segment?

Nish Neelalojanan: Large memory is completely overshadowing any CPU prices, right? Memory and storage. The CPU is not anymore determining your system price point, and when you're paying that amount, people will obviously start upgrading. Now, that said, there are still Panther Lake systems you can get below $1,500 out there, right? It's going to be dependent on OEM. It's going to be dependent on markets, and even the Wildcat Lake, they'll announce a $599 starting price point. Yeah, so there are definitely designs which are coming at comparatively reasonable price points, which are available, and longer term, I think something has to give right. The over inflation, we will have to keep an eye, but if I could predict the memory market, I would be rich in stock!

Jake Roach: Let me phrase the question a little bit better, because are you making plans for a longer term, a longer term squeeze on the consumer front, because surely you're going to have to make those plans if you see the headwinds going that way.

Nish Neelalojanan: We do have products with support for DDR4 both on desktop and mobile, so Raptor Lake, you're not end of life in any of them, they're there. We'll continue to make sure that there are products which can take care of older memory technologies if they're available and cheap. Second thing is, we are making sure we are validating lower configs as well. Wildcat Lake starts at 8GB, Wildcat Lake is a single channel product, so there are products which can leverage with low memory and give reasonably good performance, so we are doing everything we can from our perspective to be able to help in any small way. But like I said, when CPU becomes the least relevant from an overall BOM (Bill of Materials) perspective, because it's so expensive. Then we also have CPUs you can buy out into that.

Jake Roach: Speaking of memory, I don't know if you had any involvement with half ranked? Is that what they call them, half ranked DIMMs from ASRock? It was with ASRock and Intel.

Nish Neelalojanan: I am not familiar with that, but we are working with a lot of indigenous memory suppliers to validate them, so we’re doing everything we can in terms of it's not just one, two, or three. If there are some local specific memory vendors, but like in PRC, and now Indonesia is even bringing up a couple of them. We're trying to validate as much as we can, so there's enough choice that people can get pockets of relief. Right? We are looking at UFS for a longer-term horizon, so that every little thing helps, right?

Jake Roach: Absolutely. I appreciate you taking the time and talking over everything. I'm very excited to see the G3 chips in action. I saw them yesterday at the Acer showcase, and I played a little bit of Forza Horizon 6, and these are pretty good.

Nish Neelalojanan: With G3 at least we're putting out some latest and greatest stuff, and in terms of a lot of these, it's not necessarily exclusive. We're broadly available, the 12 Xe on the PC side, and on the handheld, it's not like limited to one OEM. Unlike some people who hold it back, just only give it to one OEM.

Jake Roach: So all these handhelds, I believe all the ones that announced are all Windows-based handhelds. Is there consideration for Linux? How much consideration or weight do you put on that, given things like Steam OS proper?

Nish Neelalojanan: So highest level stuff we announced now is Windows based, but you can take those devices and install… and I'm sure you would imagine we would continuously want to make sure that those experiences are reasonable for end users, and we are, we would talk more about as we get closer to something, but we are exploring beyond Windows, and as we get closer, we'll talk more about.

[Session ends]

Intel recognizes the memory squeeze that’s been a plague on the PC market for the past several months. While highlighting options like Wildcat Lake and older Raptor Lake options, Intel’s Nish Neelalojanan, senior director of product management for Intel’s Client Computing Group, sat down with Tom’s Hardware at Computex 2026 to discuss the company’s outlook on the computing market, ranging from Nvidia’s recent RTX Spark announcement to ongoing memory shortages, saying “something has to give” with the latter.

“Longer term, I think something has to give, right? The over-inflation, we will have to keep an eye out,” Neelalojanan told me. “But if I could predict the memory market, I would be rich in stock.”

I asked Neelalojanan more specifically if Intel was planning around memory shortages and making any adjustments to its strategy going forward. And the answer, surprisingly, is yes, though not in the way you might expect. Neelalojanan pointed to Raptor Lake and Wildcat Lake as products that address memory shortages currently, and said that the company will continue to support products on older memory standards as long as it makes sense.

“We do have products that support DDR4 on both desktop and mobile. Raptor Lake, we’re not end-of-life-ing any of them; they’re there. We’ll continue to make sure that there are products which can take care of older memory technologies if they’re available and cheap,” Neelalojanan told me. “Second thing is, we are making sure we are validating lower configs [for Wildcat Lake] as well. Wildcat Lake starts at 8GB. Wildcat Lake is a single-channel product, so there are products which can leverage low memory and give reasonably good performance.”

Wildcat Lake, and entry-level laptop designs more broadly, have been a big focus of Computex. Presumably in response to the MacBook Neo, Intel, of course, has its Wildcat Lake options, but Qualcomm is targeting that market, as well, with its new Snapdragon C chips. AMD doesn’t have a product targeting this market of sub-$600 laptops quite yet, but we plan on asking the company about its plans this week at Computex.

We’ve seen a shift toward cheaper options on the desktop, as well. AMD just reintroduced the Ryzen 7 5800X3D and launched the Ryzen 7 7700X3D, two CPUs that use older architectures. Under normal circumstances, they’d be unamusing at best. Under current circumstances, they’re putting components into a market that’s begging for them.

“Large memory is completely overshadowing any CPU prices, right, memory and storage… CPU is not any more determining your system price point,” Neelalojanan said. “We are working with a lot of indigenous memory suppliers and validating them, so we’re doing everything we can… it’s not just one, two or three. If there are local-specific memory vendors, like in [China] and now Indonesia is even bringing up a couple of them. We’re trying to validate as much as we can so there’s enough choice that people can get pockets of relief.”

Intel didn’t, however, say that it’s reintroducing any products along the lines of the Ryzen 7 5800X3D 10th Anniversary Edition. At the moment, it seems Intel is focused more on supporting DDR4-based options and keeping them on the market, at least until the memory squeeze loosens its grip.

It is day three of Computex here in Taipei! With most of the big-name keynotes out of the way, we're traversing the show floor non-stop to bring you the latest, greatest, and weirdest from all your favorite hardware vendors.

Computex 2026: Headlines so far

• Microsoft Surface Laptop Ultra weilds Nvidia's RTX Spark superchip with 128GB of RAM
• Nvidia lays out RTX Spark roadmap for laptops and desktop PCs at Computex 2026
• Nvidia unveils RTX Spark Superchip for laptops and desktop PCs at Computex 2026
• Intel details long-awaited Crescent Island AI GPU at Computex, boasts up to 480 GB of LPDDR5X
• Intel Xeon 7 ‘Diamond Rapids’ CPUs officially launching in 2027 on Intel 18A-P
• Intel Xeon 6+ ‘Clearwater Forest’ puts 18A in the data center with up to 288 cores
• AMD’s formerly China-exclusive Radeon RX 9070 GRE goes global for $549 on June 2
• AMD confirms AM5 support through 2029
• AMD brings back Ryzen 7 5800X3D, launches Ryzen 7 7700X3D
• Dell XPS 13 targets MacBook Neo with Intel's Wildcat Lake
• Alienware debuts 39, 34-inch OLED gaming monitors

Computex 2026: Live updates

Well, good morning, and a very (very) warm (and humid) welcome to our Computex 2026 live blog. Stephen from the UK here to see you through the first few hours of Monday. As mentioned, it has already been a jam-packed first day!

There's really nothing like Taipei during Computex:

Nvidia enters the laptop and desktop market

If you're just joining us, then welcome. It is evening in Taiwan and there's a lot happening. Headlines from the first day of Computex include Nvidia's incursion into the desktop PC and laptop market by way of its new RTX Spark Superchip. RTX Spark is a Windows on Arm platform for laptops, which Nvidia claims is the most efficient every built. Top-spec chips offer 20 Arm CPU cores, a Blackwell GPU with 6144 CUDA cores, 128GB of LPDDR5X RAM, and up to 300 GB/s of memory bandwidth.

• Nvidia unveils RTX Spark Superchip for laptops and desktop PCs at Computex 2026

Surface Laptop Ultra

One of the first companies to get behind Nvidia's new RTX Spark, understandably, is Microsoft. The company has unveiled a new Surface Laptop Ultra, effectively its own version of the MacBook Pro. It features a 20-core CPU, Blackwell GPU, 128GB of unified RAM, and more. That's housed in a 15-inch chassis with a mini-LED display, replete with HDMI, USB-C, USB-A, and an SD card reader.

• Microsoft Surface Laptop Ultra weilds Nvidia's RTX Spark superchip with 128GB of RAM, 20 Arm CPU cores, and a Blackwell GPU

Intel Crescent Island

Somewhat overshadowed by Nvidia, Intel has unveiled its new Crescent Island AI GPU, featuring up to 480GB of LPDDR5X memory. The data center GPU is "built for agentic AI," is built on Intel's Xe3P architecture, but details about raw specs are scant at this stage.

• Intel details long-awaited Crescent Island AI GPU at Computex, boasts up to 480 GB of LPDDR5X to combat memory shortages

Radeon RX 9070 GRE

AMD's China-exclusive Radeon RX 9070 GRE is going global, with a $549 price tag when it launches on June 2. This GPU sits right between the 9060 XT and the RX 9070, and you'll be able to catch benchmarks on Tom's Hardware very soon.

• AMD’s formerly China-exclusive Radeon RX 9070 GRE goes global for $549 on June 2

Jake is hungry!

"You ever get to the end of the day and realize you haven't eaten a thing." A quick look behind the scenes at Tom's Hardware, where CPU analyst Jake Roach has just realised that he hasn't eaten anything today. It's 8pm.

AM5 lives on

After previously only committing to supporting its AM5 platform through 2027, the company this week confirmed that it is actually going to support AM5 through 2029, with both Zen 4 and Zen 5 likely to see two further generations of CPU release. It's unclear if this is 2029 will mark the end of the line for AM5.

• AMD confirms AM5 support through 2029

The return of a legend

AMD has announced it will bring back its legendary Ryzen 7 5800X3D, and is also launching a Ryzen 7 7700X3D to fight the rising price of PC building. The latter is a downclocked version of the 7800X3D for AM5 platforms, but the real headline is the 5800X3D, which supports DDR4 RAM and, in theory, should give users a more affordable way to build a potent gaming PC on AM4.

• AMD brings back Ryzen 7 5800X3D, launches Ryzen 7 7700X3D to combat rising component prices

Dell comes after the MacBook Neo

This $699 XPS 13 laptop built around Intel's Wildcat Lake platform is the company's answer to the popular MacBook Neo. Featuring between 8-32GB of RAM, a 13.4-inch display, and up to 1TB of storage, it comes with either the Intel Core 5 320 or an upcoming Intel Core Ultra 7 355 variant.

• Dell XPS 13 targets MacBook Neo with Intel's Wildcat Lake — $699 starting price, $599 for students

DLSS 4.5

Nvidia has confirmed that DLSS 4.5 Ray Reconstruction, an advanced denoiser for better ray-tracing and path-tracing image quality when it releases later this year. Nvidia says it can process 35% more input data and uses 20% more paramaters using the same compute budget as the previous-generation.

• DLSS 4.5 Ray Reconstruction update arrives in August for better ray tracing visuals — broader training data set and second-gen transformer architecture combine for improved image quality

Qualcomm hands on

Qualcomm's new $300 and up ARM laptops come with a mystery eight-core CPU and active cooling. Rocking the new Snapdragon C chip, our very own Paul Alcorn made a discovery that perplexed even the Qualcomm representative on the floor...

• We went hands-on with Qualcomm's new '$300 and up' ARM laptop platform with mystery eight-core CPU — active-cooled Snapdragon C laptop surfaces in Acer Aspire Go 15

A big EXPO boost

AMD is launching a new automatic memory overclocking feature. EXPO Ultra Low Latency promises a 13% uplift in performance compared to standard DDR5 JEDEC speeds, and a 4% uplift over existing EXPO.

• AMD promises 13% uplift with new EXPO ‘Ultra Low Latency’ overclocking on DDR5 DIMMs — automatic memory overclocking delivers 4% improvement over standard EXPO, says AMD

Intel not resting on its laurels

Speaking to Tom's Hardware in response to news about Nvidia's RTX Spark, Intel says it treats all such developments with "a healthy does of paranoia," but touted the virtues of x86, warning of compatibility, DRM, and other issues that inevitably follow Arm CPUs entering the market.

• Intel warns it has 'a healthy dose of paranoia' over Nvidia entrance into PC market — company says RTX Spark is 'great for the market' while touting the virtues of x86

Supermicro makes an appearance

Computex isn't all about consumer hardware, with plenty of B2B and industrial hardware on display too. We got a look at Supermicro's new Vera Rubin NVL72 rack, replete with a new type of cooling that the company says offers 1,000 times higher electrical impedance than standard.

• Supermicro shows off Vera Rubin NVL72 rack with all-new type of coolant — company claims coolant offers 1,000 times higher electrical impedance over standard cooling

A staggering 5090 from Asus

To celebrate 20 years of its ROG brand, Asus has unveiled a monster new ROG Astral GeForce RTX 5090 Edition 20, which includes a wraparound AMOLED display. There's also a 3,000W power supply, a new NUC, a PC case, peripherals, a gaming chair, and more.

• Asus' monstrous ROG Astral GeForce RTX 5090 Edition 20 includes expansive curved AMOLED display — also debuts 3,000W power supply and striking PC case

See what happened at the show before the show

Computex starts before the show floor opens. While it's nighttime in Taipei, you can still take a look at everything we saw early with our Day Zero Wrap Up.

You'll learn more about chips from Intel and AMD, monitors from Acer and Alienware, and, of course, learn a ton about Nvidia's RTX Spark system on a chip.

That should hold you over until the show floor doors open and we get into even more of the nitty-gritty.

Read: Computex 2026 Day Zero Wrap-Up: Nvidia launches RTX Spark Superchip assault on laptop and desktop markets, Intel readies Xeon 6+

Vincent van Gogh, on a laptop

MSI is taking its Prestige 14 Flip AI+ and putting some prestige art on it. The company says the laptops are "inspired by The Starry Night and Starry Night Over the Rhône". That language makes it unclear if they're exact duplicates of the paintings, but either way, they don't look like anything else we've seen lately.

Asus ROG Xbox Ally X20 finally brings an OLED screen

Among the many twentieth-anniversary branded Asus ROG gadgets the brand is releasing is a new version of the Asus ROG Xbox Ally X.

The ROG Xbox Ally X20 bundle includes an updated version of the handheld, with a clear shell, OLED display, TMR joysticks, and a transforming D-Pad with four and eight-way movement. It still has the same AMD Z2 Extreme processor as its predecessor.

ROG XREAL R1 Edition 20 Gaming AR Glasses, with a 171-inch, 240 Hz virtual display at 4 meters.

No pricing information is available just yet.

Who ISN'T having a milestone anniversary?

Lots of companies and brands at Computex seem to have started in years that end with 6.

• Asus ROG has a 20th anniversary product line
• MSI is celebrating 40 years, marked by the Titan 18 HX Dragon Edition Draco Epic laptop (pictured above).
• Gigabyte marked 40 years at the end of May, and is celebrating with its Infinity Design lanauage, including a GPU with rounded edges.

So consider this your reminder to at least get a card for your or a loved one's anniversary. Clearly everyone is celebrating.

How Intel is reacting to RTX Spark

With Nvidia's RTX Spark announced, CPU manufacturers are sizing up the field.

When we sat down with Tom’s sat down with Nish Neelalojanan, senior director of product management for Intel’s Client Computing Group, he told us how Intel is reacting:

“Nvidia puts out great products, right? And they know how to do gaming, they know how to do all these different things. So we always take everything with a healthy dose of paranoia, but we are also very, very confident with our products." He also pointed out Arm chips for Windows have typically had compatibility issues.

Read more: Intel warns it has 'a healthy dose of paranoia' over Nvidia entrance into PC market — company says RTX Spark is 'great for the market' while touting the virtues of x86

An 18-inch laptop for the rest of us

Usually, an 18-inch laptop is a massive workstation or gaming rig. But at Computex, Acer has an 18-inch system, the Aspire 18 AI designed for everyday use. Above, it's pictured next to a 16-inch PC.

That 18-inch screen has just a 1920 x 1200 resolution, but for people who turn up the font size to read (no shame in it!), it may still help. The refresh rate tops out at 165 Hz.

Specs include a CPU up to an Intel Core Ultra 9 386H, up to 32GB of DDR5 RAM, up to 2TB of SSD storage, and Wi-Fi 7 support. Acer claims 22 hours of battery life. And hey, there's room, so you get a number pad.

Like much of what we're seeing at Computex, we don't have a price. But if you've been jonesing for a big screen without a discrete GPU, it is on the way.

AMD had to reengineer the Ryzen 7 5800X3D for a rerelease

AMD's David McAfee shared the story behind the Ryzen 7 5800X3D, and why it took so long to come to market. Apparently, AMD had plans to bring back the chip earlier, but the silicon bonding process TSMC had previously used was no longer available, McAfee says. That led to some additional development time in order to get the CPU into shape, which happened to line up with the 10th anniversary of the AM4 socket. - Jake Roach

Get ready for Intel's Computex keynote

Intel's CEO Lip-Bu Tan is set to take the stage at Computex in just under an hour, and we expect about a 45-minute keynote from the executive, followed by a Q&A session that Tom's Hardware is attending. Although we've already seen most of Intel's announcements, ranging from the G3 Extreme Range to a Diamond Rapids tease, it's possible Tan could drop some hints about next-gen Nova Lake chips during the keynote. - Jake Roach

• Watch Intel's Computex 2026 keynote here — CEO Lip-Bu Tan takes the stage in Taipei at 10:30pm PT on June 1

Intel's 3D V-Cache competitor?

Tom's Hardware attended a Q&A session with Intel CEO Lip-Bu Tan, as well as a panel of executives, including Alex Katouzian, a Qualcomm veteran who recently joined Intel's ranks. We asked Intel about its supposed 3D V-Cache competitor, rumored to be called bLCC or Big Last Level Cache, and Katouzian shared the following:

"When I first came in and started reviewing road maps for the team, I was very pleasantly surprised. So, stay tuned, a very strong roadmap coming, and we will be gunning for that section of the market as well. And so, please stay tuned," Katouzian told Tom's Hardware.

Phison has demoed its future PCIe 6.0 SSD controller in the past, but the earlier displays last year merely showed the chip on a large development. Development of the new X3 controller has obviously moved forward well, as the company had two reference SSDs on display in its booth here at Computex.

Phison says these new SSDs deliver up to 28 GB/s of sequential read/write throughput and an incredible 6.8 million IOPS, easily beating anything available on the market. Stay tuned for our full write up.

Stephen checking in

Well a very good morning from day 2 of Computex! Stephen here to see you through the next few hours.

Timing is everything!

Computex is just like comedy, timing is very important! Coordinating a team around the globe is pretty hectic, so here's some insight into how tricky it can be. It's 10:24am in the UK, but our team on the ground in Taipei have already been at it all day, where it's currently 5:24pm. Of course, our U.S. readership and staff are just waking up. Lots of companies are still working in Eastern or even Pacific time too. A lot of plates in the air.

Snapdragon makes an appearance

We haven't heard too much from Qualcomm this week, with Nvidia dominating the headlines thanks to RTX Spark. However, this Asus Ascent QN10 is a nifty new Mini PC with Snapdragon X2 Elite, which QC claims is the world's first to deliver 80 TOPS through its NPU.

Noctua's latest cooling efforts

For those who want to squeeze every last drop of power and temperature optimization from their CPU, Noctua has announced new thermal pads for AMD chips. Made in partnership with Carbice, these pads are for AM4 and AM5 Ryzen CPUs and are made from carbon nanotubes to improve thermal conductivity.

• Noctua announces new thermal pad for AMD chips in partnership with Carbice — product will work with processors in AM5 and AM4 sockets

Gigabyte's latest and greatest monitors

Gigabyte has unveiled a new series of Aorus Elite gaming monitors. Ranging in size from 27 to 32 inches, three of them feature fourth-generation Tandem WOLED technology for improved color and brightness. The fourth is a mini-LED monitor.

• Gigabyte debuts fourth-gen Tandem WOLED and multi-mode Mini LED gaming monitors — 27 to 32 inches, up to 480 Hz, and up to 5K resolution

Asus’ ROG Harpe II Extreme Edition 20 hands on

Asus is going big to celebrate the 20th anniversary of its Republic of Gamers brand. Alongside a monster RTX 5090 and a 3,000W PSU, there are new peripherals including this Asus ROG HArpe II Edition 20 gaming mouse. It features a gold logo and scroll wheel, as well as gold accents. A little garish for some tastes, it'll cost an eye-watering $259.99.

• Hands-on with Asus’ ROG Harpe II Extreme Edition 20 gaming mouse – 24K gold and a 65K sensor

Relive Intel's keynote

Intel held its Computex keynote overnight, with CEO Lip-Bu Tan taking to the stage. You can relive the keynote below!

The latest in cooling from Frore

Frore has been showing off its latest in solid-state cooling tech. Its AirJet Mini is out here cooling Intel's Wildcat Lake laptop reference design. With 15W of sustained power and just 11.3 mm in total thickness, could it give the MacBook Neo a run for its money?

• Frore System’s solid-state AirJet Mini cools Intel’s Wildcat Lake laptop reference design – 15W of sustained, fanless cooling helps MacBook Neo competitor reach a svelte 11.3 mm, remain silent

Take our quiz!

'The single most important tool of humanity'

Nvidia CEO Jensen Huang says the company wants to 'reinvent the single most important tool of humanity' with its new RTX Spark. The company unveiled its new chip for desktops and laptops at the start of this week.

• Jensen Huang says Nvidia wants to 'reinvent the single most important tool of humanity' with RTX Spark — Nvidia CEO touts support of 'literally every computer maker in the world' for its agentic AI PC platform

Favorite Computex announcement so far?

Cooler Master's MasterDimm

Unveiled ahead of Computex, this Cooler Master MasterDimm is a collaboration with G.SKILL that brings active cooling to DDR5 RAM. No word on just how big those sticks are yet...

New from Gigabyte

Gigabyte is another vendor celebrating a major anniversary at Computex, specifically 40 years in the game. There's new motherboards, GPUs, and a monster 1,600W power supply.

• Gigabyte showcases new Infinity products for its 40th anniversary — X870 Infinity Next halo motherboard boasts metal 3D-printed elements, Aero Wood goes dark, MicroATX Stealth boards, Infinity-style GPUs extend down the product stack

Phison shows off its new controller

Down at Phison, we took a look at its new PCIe 6.0 SSD controller, the X3. The company touts sequential speeds of up to 28 GB/s and 6.8 million IOPS in random read/write workloads. There were also benchmarks on display for a new DRAM-less PCIe 5.0 SSD controller. Get the details here:

• Phison shows PCIe 6.0 X3 SSD controller with 28 GB/s of bandwidth and 6.8 million IOPS, supports 2 petabytes per drive— also new power-sipping E37T SSDs for PCIe 5.0 systems consume a mere 4.5W

You don't know the HAF of it

More from Cooler Master, where we took a look at the company's new cases, fans, and coolers. The new HAF500 case supports up to E-ATX motherboards, dual-GPU setups, and plenty of cooling.

Asus ROG Rapture GT-BE98 Pro Edition 20 gets decked out in black and gold

Asus just launched the ROG Rapture GT-BE98 Pro Edition 20, the 20th-anniversary edition of its existing ROG Rapture GT-BE98 Pro. The overall design of the new router is identical, but the stealth black look is now accentuated with gold trimmings. You can even see gold plating beneath the clear plastic window on top of the router, along with a 20th anniversary badge finished in gold.

While you can expect the same blazing performance as the ROG Rapture GT-BE98 Pro, the ROG Rapture GT-BE98 Pro Edition 20 also includes an exclusive Signature Edition 20 web interface for configuring the router.

MSI Claw 8 EX AI+ joins the growing number of handheld gaming PCs

There's a new competitor to take on the likes of the Steam Deck, ROG Ally, and Legion Go 2. The MSI Claw 8 EX AI+ is a fresh entry using a 14-core Intel Arc G3 Extreme CPU and an Arc B390 GPU. The handheld can also be decked out with up to 32GB of RAM and up to 1TB of storage.

The design looks somewhat unorthodox, with the 8-inch 1080p IPS display jutting well below the flanking controllers. The display is spec'd for a 120 Hz refresh rate and maxes out at 500 nits. Rounding out the main features is an 80 WHr battery inside the 1.3-pound package.

Best Buy already has a product page for the Claw 8 EX AI+ on its website, listing the 32GB/1TB configuration at $1,699.99. However, the handheld is only shown as "coming soon" rather than being available for preorder.

Asus ROG Rapture GT-BN98 Pro will be among the first Wi-Fi 8 routers on the market

If you want to be on the bleeding edge in wireless networking, you won't have to wait much longer for Wi-Fi 8 routers. The first Wi-Fi 8 router coming from Asus will be the ROG Rapture GT-BN98 Pro, which is a gaming router aimed at the high end of the market.

We must caution that Wi-Fi 8 routers won't result in another huge leap in theoretical performance over existing Wi-Fi 7 routers. Instead, optimizations with the standard will make it so that real world performance and range will far exceed what's possible with current hardware. We should also see even longer range for IoT devices, epecially those sitting at the far reaches of the coverage for your home router.

The ROG Rapture GT-BN98 Pro will also include a wide range of LAN/WAN ports, including two 10 GbE ports and four 2.5 GbE ports.

• Asus unveils its first Wi-Fi 8 router — ROG Rapture GT-BN98 Pro offers up to 2x real-world throughput uplift over Wi-Fi 7

We go hands-on with the Acer Predator Atlas 8 Arc G3 gaming handheld

Last week, we brought you news that Acer was working on a Predator Atlas 8 gaming handheld. Well, we got a chance to get a hands-on with the device at Computex, and it's quite impressive.

The Predator Atlas 8 uses Arc G3 and Arc G3 Extreme processors paired with an Arc B370 or B390 iGPU. Systems come with an 8-inch 1200p 120 Hz variable-refresh-rate display rated for up to 500 nits of brightness. An 80 WHr battery should help extend your gaming runtime, and Wi-Fi 7 and Bluetooth 5.4 are included in the mix.

At 1.79 pounds, the Predator Atlas 8 slots in between the Legion Go and the Steam Deck OLED in weight.

Intel's Xeon 6+ in the flesh

We stopped by Intel's demo suite, and the company had a Xeon 6+ chip, along with a wafer, hanging on the wall. This is Intel's first time using 18A in the data center, with Xeon 6+ now sporting up to 288 Darkmont E-cores. You can learn more about it in our Xeon 6+ write-up and go behind the scenes with our Xeon 6+ interview transcript on Tom's Hardware Premium.

Day 3

Good morning and welcome to day three of Computex! I say day 3, but as we've explained before timing is tricky here. In Taiwan day three is almost over, but for our global audiences in places like the UK and U.S., it's just beginning! - Stephen Warwick

Some highlights from Acer

We dropped by Acer to see what the company has to offer at Computex this year. We saw the new Acer Swift Spin 14 AI tablet, the new Predator Atlas 8, and more!

Jensen will sign anything

Everyone knows that if you see Nvidia CEO Jensen Huang at Computex, chances are he'll sign something for you. How about this epic Nvidia GTX 1080Ti Founders Edition?

Noctua's AIO in all its glory

We've been hearing a lot about Noctua's entry into the AIO market for some time. The company is back at Computex 2026 and has finally revealed specs, pricing, and release date. Coming on June 16, pricing should be around $250 (It is listed at 220 euros), with more expensive 360mm and 420mm options available. The NL-LC1 features Asetek's Emma V2 pump and NF-A12/14 fans.

• Noctua's first-ever AIO features a silenced Asetek Emma V2 pump and NF-A12/14 fans — 240mm NL-LC1 starts at around $250, could cost $325 for 420mm cooler

The first 8K ultra-wideband gaming keyboard

Cherry's gaming branch Cherry XTRFY has unveiled the first 8K ultra-wideband gaming keyboard at Computex. With a 70% layout, the technology should be more reliable than 2.4GHz wireless. That means a more stable connection that is less vulnerable to interference from other wireless devices.

• Cherry XTRFY launches first 8K ultra-wideband gaming keyboard — featuring more compact 70-percent layout

Corsair's new mouse feat. Stream Deck

New from Corsair is this Nightsword v2 Wireless SD Stream Deck gaming mouse. Striking name aside, you can map its buttons to Stream Deck features, eight in all, so that you can control streaming functions without taking your hand off the mouse. It's a similar philisophy to the Scimitar Elite Wireless SE. However, the Nightsword also comes with a unique dedicated Stream Deck Launch button.

• Corsair shows off gaming mouse with dedicated Stream Deck launch button — wireless mouse also gets almost 50 hours of 8K battery life

New from NZXT

We stopped by NZXT to see what's news. The company showed off new RGB fans, cases, and more.

Counterfeit DRAM

Tom's Hardware spoke to G.Skill and V-Color at Computex. The latter confirmed to us that it has seen an influx of counterfeit DRAM hitting markets in China, to the extent that it is negatively impacting sales.

• Counterfeit G.Skill and V-Color DDR5 modules hit Chinese marketplaces, impacting company sales — cheap contraband memory using identical PCBs and heat spreaders almost impossible to spot

A long day for Jensen

Nvidia CEO Jensen Huang is one of the main attractions at Computex, and is often mobbed wherever he goes, shutting down booths or even entire floors here in Taipei. Here he is enjoying some brief respite at the Gigabyte booth with a beer and some barbecue.

Taipei drone show

The evening skies in Taipei lit up with a drone show to celebrate Computex, check it out!

Lian Li's new Edge PSUs

Take a look at Lian Li's new Edge Platinum V2 PSUs, equipped with LED dust indicator, magnetic filter, snap-on fan, and a USB header hub. There's also the trademark 90-degree power connector.

The claaaaaaw

The new MSI Claw 8 EX AI+ is an 8-inch handheld that features a 120 Hz display and new ergonomic grips. Bathed in a striking 'Void Purple' finish, our immediate hands-on yielded some impressive performance.

• MSI Claw 8 EX AI+ brings Intel Arc G3 Extreme to handhelds — 8-inch, 120 Hz display and new ergonomic grips

AMD reacts to Nvidia RTX Spark

AMD is acting confident in the face of Nvidia's new RTX Spark announcements.

"I’m really excited that Nvidia has joined the game. You know, we were the only game in town for almost two years now, and the large local memory is becoming super critical in the agentic AI [workloads],” said AMD’s Rahul Tikoo, senior vice president and general manager of AMD’s client business. at Computex “I'm actually happy to see Nvidia join the race for these great products.

Comparing the specs, he suggested that "Gorgon Halo, which is coming out in Q3, is going to be a better product.”

We'll see how these platforms shake out later this year.

Read more: AMD executives react to Nvidia’s RTX Spark — ‘you’re just wrong if you don’t get a Strix Halo notebook’

Sizing up the Dell XPS 13 and MacBook Neo

Which of these systems is thicker? Trick question: both are half an inch thick. At Computex, our own Jake Roach saw the two together at Dell's booth.

The Neo's bottom is thicker, while Dell's is a bit more equal. And the XPS has a slightly rounded bottom, making it appear slightly thinner than Apple's blockier design style. But both list the exact same height, and the spec sheets are identical.

The XPS, however, is lighter than the MacBook Neo, at 2.2 pounds, compared the Apple's 2.7 pounds.

See all of the photos in the gallery above.

MSI adds an internal SSD slot to its flagship Wi-Fi 7 router

Wi-Fi 8 is just around the corner, but there’s still plenty of life left in the Wi-Fi 7 standard. MSI is proving that with a new flagship Wi-Fi 7 router called the RadiX BE19000. At first glance, the RadiX BE19000 looks like any other high-end gaming router, complete with eight antennas that give it an arachnid-like appearance.

However, the RadiX BE19000 hides a secret within — it features a PCIe SSD slot, making the router what MSI calls “NAS Lite.” You can add your own M.2 SSD to enable PC backups or simply to share files across your network.

You still get all the usual trimmings, like tri-band Wi-Fi, dual 10 GbE ports, and four 2.5 GbE ports. In addition, MSI says that the RadiX BE19000 is compatible with its proprietary mesh standard, allowing you to expand your network with compatible routers and access points.

Read more: MSI unveils latest set of WiFi 7 gaming routers touting ultra-fast speeds — flagship RadiX BE19000 model comes with a built-in SSD slot for 'NAS Lite' experience and wireless speeds up to 19 Gbps

Do your science homework

We talked a bit about Noctua's new AIO cooler in this live blog, but one thing we didn't mention: just how much homework they show. The company is ready to defend its doctoral thesis.

If you're ever at Computex, need to rest and do some not-so-light reading to explain what a thermosiphon or a flooded condenser is, Noctua has your back. You can see some of it in the gallery above, and believe me, that is just some of it.

Here ends Computex

Good morning folks, Stephen here to announce that we are signing off our Computex coverage for 2026. At least, our live correspondence from the floor. There's still plenty of news and insight to come from our conversations, but we'll be winding up this live blog soon. It'll remain on the site so you can look back and trawl through any announcements you may have missed, but thank you for joining us for another great year!

Intel has confirmed several details about its next-generation Xeon 7 CPUs, codenamed Diamond Rapids, which are now officially slated to launch in 2027. Announcing its E-core-only Xeon 6+ chips at Computex, Intel teased that Diamond Rapids will support PCIe 6.0, pack 50% more cores than Xeon 6, and double the memory bandwidth. Intel is building Diamond Rapids chips on the Intel 18A-P node, which is a refined version of 18A that Intel demoed just last month.

Although Intel never formally announced a release window for Xeon 7, we originally expected to see the chips this year – a timeframe that became increasingly unlikely as news about Diamond Rapids dried up. Now, Intel has officially confirmed Diamond Rapids is arriving next year, meaning AMD will have a head start with its next-gen EPYC Venice CPUs built on the Zen 6 architecture, which are still (at the moment) slated for release this year.

Like Venice, Intel has confirmed Diamond Rapids will support PCIe 6.0, as well as double the memory bandwidth of Granite Rapids. Last year, Intel confirmed it canceled an 8-channel memory variant of Diamond Rapids to focus exclusively on the 16-channel design. Granite Rapids-AP (12-channel) topped out at 614 GB/s of memory bandwidth, while Granite Rapids-SP (8-channel) topped out at 409 GB/s. Depending on the comparison point — Intel didn’t clarify — you’re looking at topline memory bandwidth of at least 1.2 TB/s or 818 GB/s, respectively. Second-generation MRDIMM support, however, means that bandwidth could climb to upwards of 1.6 TB/s.

We can do similar math with core counts, looking at the top-end 6980P from Granite Rapid-AP at 128 cores. A 50% increase in core count brings us to 192 cores. Diamond Rapids has been rumored to climb up to 256 cores, with a 512-core dense version planned later. Intel is suggesting those rumors are false, though no hard specifications are confirmed yet.

The big question is what microarchitecture those cores will use, and if they’ll support Hyper-Threading. Intel removed Hyper-Threading from the Lion Cove P-cores in Lunar Lake and Arrow Lake, and kept it out of the Cougar Cove P-cores in Panther Lake. Naturally, if Xeon 7 uses either of those P-core microarchitectures, we’d also expect the chips to lack Hyper-Threading. Adding to the speculation were some comments Intel made in its January earnings call, where it said that it “will also reintroduce multi-threading back into our data center road map.”

Recently, however, Intel documents have suggested Diamond Rapids will use Panther Cove, an as-of-yet unreleased microarchitecture. We should know for sure what’s going on under the hood of Diamond Rapids soon. "We expect to share more on Diamond Rapids in the late summer at Hot Chips, so stay tuned there,” an Intel spokesperson shared in a Q&A with Tom’s Hardware.

Perhaps the most significant reveal in this tease is that Diamond Rapids is using Intel 18A-P. We’ve known for a while that the first 18A CPUs in the data center would be Xeon 6+, which Intel has now officially launched. 18A-P is a revision of 18A, but Intel has already demonstrated that it’s quite a significant revision.

Intel claims 18A-P delivers 9% higher performance at the same power as 18A, or an 18% power reduction at the same performance level. Intel says it also improved reliability and tweaked voltage behavior, making 18A-P a much more mature revision of 18A, likely in a bid to attract external customers for Intel Foundry.

Intel is facing off against AMD’s Zen 6 Venice CPUs, which we expect to learn more about at AMD’s Advancing AI event in July. So far, AMD has confirmed that Venice will launch with up to 256 cores, 1.6 TB/s of memory bandwidth per socket, and a 70% jump in gen-on-gen performance. There’s still a lot we don’t know about Venice and Diamond Rapids, but from the initial teases, Team Red is looking like the leader.

That would make sense. Although Diamond Rapids is a significant release for Intel, the company has continually reiterated the importance of Coral Rapids, the generation that will follow Xeon 7 on Intel’s road map. We expect to see Coral Rapids in 2028, featuring SMT, and Intel has said that it’s looking into ways to accelerate the Coral Rapids rollout.

Intel is returning to the data center with Xeon 6+, now harnessing the power of Intel 18A. After revealing Xeon 600 chips for workstations earlier in the year, Intel is turning back to the data center with Xeon 6+, an E-core-only design previously known as Clearwater Forest. The flagship Xeon 6990E+ is designed for compute density, packing in 288 Darkmont cores with 576 MB of L3 cache, with support for dual-socket systems, taking the core count up to 576. Intel claims the 6990E+ delivers an average 30% performance per thread improvement compared to AMD’s 192-core Epyc 9965, as well as up to 30% better power efficiency.

We’ve heard a lot about Clearwater Forest leading up to this launch, including a full architectural deep dive from Intel last year. As a refresher, Xeon 6+ is the culmination of Intel’s disaggregated approach to processor design over the past several generations, using a mixture of nodes and packaging techniques to achieve such high core density. On top of the silicon stack are 12 CPU chiplets built on Intel 18A, each packing 24 Darkmont E-cores without Hyper-Threading. They sit on three base tiles that hold the L3 cache and memory, which are built using Intel 3. Sandwiching this stack are two I/O chiplets built on Intel 7. Bringing the chiplets together are 12 EMIB 2.5D tiles, which are silicon bridges built directly into the substrate.

Outside of the chips, Xeon 6+ chips work with existing Xeon 6 platforms on the LGA 7529 socket (the same as Granite Rapids-AP). Intel supports both single and dual-socket systems, and with support for up to 12 channels of DDR5, running at up to 8000MT/s and 96 lanes of PCIe 5.0 (64 lanes of CXL). Those platform specs are for a single-socket system.

The chips come with a range of acronym-adorned hardware accelerators, including Intel QAT (QuickAssist Technology), DLB (Dynamic Load Balancer), DSA (Data Streaming Accelerator), and IAA (In-memory Analytics Accelerator). The flagship 6990E+ comes with 16 total accelerators, four for each type included in the architecture. Intel also expanded the chips with instructions to accelerate the SHA-512, SM3, and SM4 cryptographic algorithms, along with more robust confidential computing capabilities through Intel SGX for application isolation and Intel TDX for VM isolation.

New for Xeon 6+ CPUs is Intel Application Energy Telemetry, or AET. It’s a hardware-based telemetry tool that Intel says can provide insight on energy usage for “workloads, microservices, containers, VMS, applications and even on an individual software thread-level when desired.” Xeon 6+ CPUs are the first to support AET, and Intel says it will be available on Xeon processors going forward, specifically targeting data center providers.

Although there was some hope we’d see Intel’s long-awaited AVX10.2 with Xeon 6+, that isn’t the case. The CPUs don’t support any form of AVX10, or even AVX-512. They top out at AVX2, an Intel spokesperson confirmed to Tom’s Hardware.

Intel Xeon 6+ ‘Clearwater Forest’ specs

Intel has four Xeon 6+ designs and six SKUs total, with the top two models in the stack coming in power-limited configurations with lower base and all-core turbo speeds, but otherwise identical specs.

Before getting into the individual processors, there are some specs shared across the entire range:

• 12-channel memory at up to DDR5-8000
• Single- or dual-socket compatibility
• 96 PCIe 5.0 lanes, 64 CXL 2.0 lanes, and 6 UPI 2.0 lanes
• 1024 Intel TDX keys per CPU
• Up to 16 accelerators (four each for Intel QAT, DLB, DSA, and IAA)
• Intel AET

Compared to last-gen Sierra Forest chips, the spec that immediately stands out is TDP. With Sierra Forest, Intel topped out at 330W on the Xeon 6780E and went down as low as 205W on the 6710E. Now, 300W is the floor and 450W is the ceiling, bringing it into closer alignment with top-end TDPs from AMD’s EPYC range. As usual, however, TDP only hints at real-world power consumption, which can vary widely depending on numerous factors.

Core counts have jumped massively, as expected, but so has the amount of L3 cache. The 6990E+ has more than five times the amount of L3 cache as the 6780E. Even the 6960E+, which has 144 cores like the 6780E, has four times as much L3 cache. L2 cache remains unchanged, however. Intel is using 4MB of L2 cache per cluster of four cores. That cache is technically shared among those cores in a cluster, but you can think of it as 1MB of L2 cache per core.

Intel Xeon 6+ ‘Clearwater Forest’ performance and benchmark claims

Intel shared a variety of benchmarks for Xeon 6+, comparing the new flagship Xeon 6990E+ to last-gen Intel chips, as well as AMD’s current EPYC offerings. Overall, Intel claims a generational improvement of 2.26x compared to the Xeon 6780E, as well as 30% higher performance per thread compared to AMD’s EPYC 9965.

Starting with the generational improvement, it’s no surprise to see such a massive uplift in performance. After all, Intel is comparing the Xeon 6990E+ to a CPU that has half the threads and a 120W haircut on TDP. The Xeon 6780E that Intel is comparing its latest Xeon 6+ chip to is the flagship from the last-gen Sierra Forest range, however. On average, Intel claims a 2.26x uplift, and as you can see from Intel’s internal benchmarks, the Xeon 6990E+ offered more than double the performance of the Xeon 6780E across every workload Intel tested.

The more important metric here is performance per watt, however. The Xeon 6990E+ has a much higher TDP and denser compute, but Intel still claims an average efficiency improvement of 55%, ranging from a 30% uplift in the Stream Triad memory bandwidth benchmark up to a 79% improvement in Linpack. For these benchmarks, Intel used a mixture of dual-socket and single-socket systems, matching the configuration for the specific test (i.e. using two dual-socket or two single-socket systems rather than mixing and matching). You can see the exact configuration details in the full slide deck at the end of this article.

Given Team Red’s inroads into the data center over the last several generations, the competitive performance is perhaps more important. Intel says that the Xeon 6990E+ delivers 30% higher performance per thread, on average, compared to the EPYC 9965, as well as 30% higher average performance per thread per watt. Per-thread performance is important, absolutely, but Intel doesn’t have any data comparing average performance across the entire die to AMD’s offerings.

That’s likely due to overall thread count. Although Intel packs 288 cores in the Xeon 6990E+ compared to the EPYC 9965’s 192, AMD uses simultaneous multithreading, while Intel doesn’t. A per-thread advantage usually doesn’t directly translate to an overall performance advantage. It’s just one metric that could be important depending on the workloads you’re running. According to Intel’s benchmarks, Xeon 6+ holds around a 30% advantage in integer and floating-point throughput, and around a 38% improvement in efficiency.

Although Intel restricted hard numbers to the performance-per-thread metric, it provided a small glimpse at overall efficiency compared to the competition. At 40% CPU utilization, Intel claims the 6990E+ is up to 30% more efficient than the EPYC 9965. Assuming this chart is accurate and not some skewed visualization (that’s possible), you can see efficiency get much tighter as utilization increases.

Intel doesn’t have benchmarks comparing Xeon 6+ to designs based on the ARM instruction set, which is becoming an important comparison point. Just recently, we saw the first benchmarks of Nvidia’s Vera CPU break cover. The company, however, says that it thinks “[Xeon 6+] compares very favorably" to ARM-based options.

Full Intel Computex 2026 Xeon 6+ presentation