⚡ RTL Design & Verification Engineer ⚡

Exploring the world of RTL Design, FPGA Prototyping, and ASIC Flows. Proficient in SystemVerilog, Verilog, RISC-V Assembly, and C++, I love bringing silicon ideas to life with SystemVerilog, RISC-V, and FPGA tools.

🔭 I’m currently working on RISC-V SoC Design, Verification & FPGA Prototyping 🌱 Learning SystemVerilog | UVM | ASIC Physical Design 👯 Open to collaborate on RISC-V & Custom EDA Projects 💬 Ask me about RTL, FPGA, Verilog, SystemVerilog 📫 Reach me at muddassiraliofficial@gmail.com

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