I design and evaluate RISC-V soft processors, from instruction-level datapaths to FPGA-based SoCs and RTOS execution.
My main interest is not only making a processor "work," but understanding why each microarchitectural choice changes timing, resource usage, and software behavior.
"μ 보λ κ²½μλ ₯μ΄μ§λ§, νμν΄ μ°Ύμμ¨ μ΄λ€μκ² κ°μ 맀겨μλ μ λλ€."
| Year | Achievement |
|---|---|
| 2025 | π ISOCC 2025 β "BASIC_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I" (Oral Presentation, IEEE Xplore) |
| 2025 | π Listed in the official riscv/learn repository as an advanced learning resource |
| 2025 | π― Achieved 1.09 DMIPS/MHz @ 50 MHz with 5-stage RV32I pipeline |
| 2026 | β‘ Scaled to 100 MHz with 8-stage pipeline, RV64IM extension |
| 2026 | π₯οΈ Successfully ported FreeRTOS to custom RV64 SoC with HDMI & keyboard |
- RV32I / RV32IM / RV64I / RV64IM soft processor design
- 5-stage to deeper 6/7/8-stage pipeline exploration
- Hazard detection, forwarding, branch prediction, trap/exception handling
- Machine-mode CSR implementation for bare-metal and RTOS support
- Multiplier/divider integration and RV64 word-operation behavior
- FPGA implementation using Vivado on Artix-7 XC7A200T (Digilent Nexys Video)
- UART-based MMIO, instruction/data memory organization, timer interrupt logic
- Timing closure experiments across different pipeline depths and clock targets
- Practical debugging with simulation, waveform analysis, synthesis, and implementation reports
- FreeRTOS porting on custom RV32/RV64 soft processors
- CLINT-style timer interrupt support (64-bit unified mtime/mtimecmp)
- Context-switch path, trap-frame handling, and scheduler behavior analysis
- RTOS latency benchmarking using Rhealstone-inspired microbenchmarks
- Dhrystone and CoreMark benchmarking on FPGA
- DMIPS/MHz and CoreMark/MHz efficiency analysis
- Resource and power comparison between RV32 and RV64 SoC configurations
- Throughput vs. frequency vs. pipeline-depth trade-off studies
A custom RISC-V soft processor project focused on running FreeRTOS on deeper pipelined RV32/RV64 cores, developed as a 5-person team at Sangmyung University.
Key topics:
- 8-stage RISC-V pipeline with HDMI and keyboard peripherals
- RV32 vs. RV64 RTOS behavior comparison
- Machine-mode trap and interrupt handling
- FreeRTOS context switching on custom hardware
- Rhealstone-style latency evaluation
An open-source RISC-V processor design series for learning, experimentation, and reproducible microarchitectural evaluation. Built on two core projects:
- basic_RV32s β A step-by-step RV32I processor roadmap from single-cycle to 5-stage pipeline with hazard forwarding, dynamic branch prediction, and exception handling. Achieved 1.09 DMIPS/MHz @ 50 MHz on Artix-7. Listed in the official riscv/learn repository and published at ISOCC 2025.
- IMA_make_RV64 β Extension of basic_RV32S to RV64IM with deeper 6/7/8-stage pipelines targeting 100 MHz. Covers M-extension integration, 64-bit datapath conversion, synchronous BRAM-compatible memory design, and multi-level forwarding across extended pipeline stages.
Key topics:
- Incremental processor design (single-cycle β multi-cycle β 5-stage β 6/7/8-stage pipeline)
- RV32I β RV32IM β RV64IM ISA extension scaling
- FPGA timing closure, BRAM inference, and resource analysis
- Bare-metal firmware and benchmark execution (Dhrystone, CoreMark)
A microarchitectural study on RISC-V ISA extension, datapath width, and pipeline depth trade-offs in FPGA-based soft processors β covering 10 variants targeting 100 MHz.
Key topics:
- RV32I β RV32IM β RV64IM evolution across 5- to 8-stage pipelines
- Pipeline depth scaling and timing closure methodology
- Performance, resource, and power trade-off analysis
- Dhrystone/CoreMark-based evaluation
RISC-V ISA extension RV32I β RV32IM β RV64IM
Pipeline scaling 5-stage β 6-stage β 7-stage β 8-stage
FPGA implementation Timing closure, BRAM inference, resource analysis
RTOS support CLINT timer, trap handling, context switching
Benchmarking Dhrystone, CoreMark, Rhealstone-style latency tests
Started as a high school student who loved building computers β founded νμ°μ μ»΄ν¨ν° 곡방, a community that grew to ~1,300 members. That curiosity about hardware led to a deeper question: "Why doesn't Korea have its own CPU?"
Studied CPU architecture during military service, built my first RISC-V processor before discharge, and presented at ISOCC 2025 weeks after. Haven't stopped scaling since β from a 5-stage RV32I @ 50 MHz to an 8-stage RV64IM @ 100 MHz with FreeRTOS running on top.
Long-term goal: Founding a Korean General Purpose Processor design company.
- GitHub: @T410N
- Email: hwctech1026@gmail.com