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CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.

SystemVerilog 31 13 Updated May 1, 2026

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,863 726 Updated Apr 14, 2026

A library for lattice-based multiparty homomorphic encryption in Go

Go 1,424 211 Updated Apr 14, 2026

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

SystemVerilog 40 41 Updated Apr 29, 2026

OpenTitan: Open source silicon root of trust

SystemVerilog 3,333 998 Updated May 1, 2026