Skip to content

Pull requests: capstone-engine/capstone

New pull request New
7 Open 1,363 Closed
7 Open 1,363 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

HPPA fix mem operands access and instruction printing HPPA Arch python bindings
#2746 opened Jun 29, 2025 by R33v0LT Loading…
2 tasks
2
1
Fix for Risc-V C.SRLI decoding (issue #2731) LLVM-generated-files RISCV Arch
#2745 opened Jun 25, 2025 by h01G3r Loading…
1 of 2 tasks
1
2
Add workflow to check for C code formatting and format all code with clang-format-18 AArch64 Arch Alpha Arch ARC ARM Arch BPF Arch CS-core-files auto-sync EVM Arch Github-files Github related files HPPA Arch LLVM-core-files auto-sync LoongArch Arch M68K Arch M680X Arch Mips Arch MOS65XX Arch ocaml bindings PowerPC Arch RISCV Arch SH Arch Sparc Arch SystemZ Arch TMS320C64x Arch TriCore Arch WASM Arch X86 Arch XCore Arch Xtensa Arch
#2744 opened Jun 25, 2025 by Rot127 • Draft
1 of 2 tasks
1
Handle zero case of R1 operand field SystemZ Arch
#2743 opened Jun 25, 2025 by Rot127 Loading…
2 tasks done
1
Warn of unused const variables.
#2668 opened Mar 29, 2025 by Rot127 • Draft
2 tasks
v6 - Beta
2
First step of dynamically updating the version from cmake CS-core-files auto-sync
#2610 opened Jan 19, 2025 by AndrewQuijano Loading…
1 of 2 tasks
1
16
initial implementation of the Sail-generated RISCV disassembler module LLVM-generated-files RISCV Arch
#2498 opened Oct 4, 2024 by moste00 • Draft
2 tasks
70
ProTip! Add no:assignee to see everything that’s not assigned.