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A nomad spreading knowledge
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A nomad spreading knowledge
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iammituraj/README.md

👋 Hi, I’m Mitu Raj from India.

👔 Founder & CEO at Chipmunk Logic™ - https://chipmunklogic.com

👀 I’m into RTL Design, Embedded Software Development, GUI/CLI Software Development for OS, Scripts, Math, Physics and much more.

🚩 Contributing to RISC-V community as an individual member at riscv.org, and in my blogs with my RISC-V CPU, Pequeno

🎓 I believe knowledge is all about sharing, and learning is permanent.

📫 Feel free to reach me - iammituraj@gmail.com or chip@chipmunklogic.com

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  1. pequeno_riscv pequeno_riscv Public

    Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

    SystemVerilog 145 13

  2. pqr5asm pqr5asm Public

    PQR5ASM is a RISC-V Assembler compliant with RV32I

    Python 19 4

  3. apb apb Public

    APB master and slave developed in RTL.

    SystemVerilog 24 2

  4. debouncer debouncer Public

    Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

    SystemVerilog 6 2

  5. fifo fifo Public

    Synchronous FIFOs designed in Verilog/System Verilog.

    SystemVerilog 25 8

  6. skid_buffer skid_buffer Public

    Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

    SystemVerilog 32 8