jge162
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Simple python scripts that calculates each module's duration.
Objective of this project was to emulate a Basketball score board, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado
Sends AI-curated digests to our club Discord server.
PHP (PDO), MYSQL and JQuery AJAX Full Project from Scratch.
Team of four CSUF seniors creating an innovative 'Automatic Waste Sorter' that utilizes advanced technology to sort waste accurately and efficiently. The system's core is driven by a Google Coral D…
Spelling checker action to check spelling in repositories / pull requests / commits
A basic GitHub repository template for initializing open source projects on a single click. Automated contributing, code of conduct, issue and pull request and readme template.
My dotfiles + system configuration for NixOS and mac
CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
Vulkan, OptiX and CUDA Interoperation Modular Rendering Library and Framework for PC/Linux/Android
ODK Central is a server that is easy to use, very fast, and stuffed with features that make data collection easier. Contribute and make the world a better place! ✨🗄✨
Johann is a simple Java library that talks to docker-compose CLI
Projects completed in Verilog while in attendance at CSUF
Embedded C projects completed while in attendance at CSUF, ADC, DAC, Matlab filter and FSM traffic light.
Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.