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1. sysver2ver sysver2ver Public

   Converting System Verilog to plain Verilog using .xml dump from Verilator

   Verilog 8 1

2. u-boot-riscv u-boot-riscv Public

   Port of u-boot to RISCV based ariane core

   C 7 4

3. efuns efuns Public

   efuns is a re-write of emacs in ocaml written by Fabrice Le Fessant

   OCaml 4

4. verilog-parser-ocaml verilog-parser-ocaml Public

   Automatically exported from code.google.com/p/verilog-parser-ocaml

   Verilog 4 1

5. LEF LEF Public

   Mirror of Cadence's LEF parser library (https://openeda.si2.org/projects/lefdefnew/)

   C++ 4 4

6. cbzone cbzone Public

   Port of the classic BattleZone arcade game to LowRISC

   C 3 1