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  1. riscv riscv Public

    Forked from ultraembedded/riscv

    RISC-V CPU Core (RV32IM)

    Verilog 1

  2. 100_days_of_RTL 100_days_of_RTL Public

    This is a repository for 100Days of RTL which consists of various Digital design circuits in verilog and verification done in system verilog

    Verilog 1

  3. VSDFlow-Steps VSDFlow-Steps Public

    Forked from shubhamgarg1299/VSDFlow-Steps

    In this repository, I have discussed the steps with the screenshots to install opensource EDA Tools for VLSI Design.

  4. OpenMIPS_all OpenMIPS_all Public

    Forked from grantae/OpenMIPS

    A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance

    Assembly

  5. OpenSTA OpenSTA Public

    Forked from The-OpenROAD-Project/OpenSTA

    OpenSTA engine

    C++

  6. SOC SOC Public

    RISC based SOC design