Skip to content
View microway199x's full-sized avatar

Block or report microway199x

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. RTL-language-BSV-BSV_Tutorial_cn RTL-language-BSV-BSV_Tutorial_cn Public

    Forked from WangXuan95/BSV_Tutorial_cn

    爆肝6万字的 Bluespec SystemVerilog (BSV) 中文教程

    Bluespec

  2. vim-resources vim-resources Public

    Vim Script 1

  3. RTL-tools-vim-verilog_systemverilog.vim RTL-tools-vim-verilog_systemverilog.vim Public

    Forked from vhda/verilog_systemverilog.vim

    Verilog/SystemVerilog Syntax and Omni-completion

    Vim Script

  4. RTL-design-riscv-e203_hbirdv2 RTL-design-riscv-e203_hbirdv2 Public

    Forked from riscv-mcu/e203_hbirdv2

    The Ultra-Low Power RISC-V Core

    Verilog

  5. RTL-tools-language-bsc RTL-tools-language-bsc Public

    Forked from B-Lang-org/bsc

    Bluespec Compiler (BSC)

    Haskell

  6. RTL-design-RISCV-BSV-refer-Flute RTL-design-RISCV-BSV-refer-Flute Public

    Forked from bluespec/Flute

    RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

    Bluespec