Skip to content
View pznikola's full-sized avatar

Highlights

  • Pro

Block or report pznikola

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. ethernet-wrapper ethernet-wrapper Public

    Chisel wrapper for Alex Forencich ethernet.

    Verilog 1

  2. chipyard chipyard Public

    Forked from ucb-bar/chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    C

  3. rocket-chip rocket-chip Public

    Forked from chipsalliance/rocket-chip

    Rocket Chip Generator

    Scala

  4. computer-engineering-resources computer-engineering-resources Public

    Forked from rajesh-s/comp-arch-sys-resources

    A curated list of Computer Engineering resources

  5. fastvdma fastvdma Public

    Forked from antmicro/fastvdma

    Antmicro's fast, vendor-neutral DMA IP in Chisel

    Scala

  6. verilog-ethernet verilog-ethernet Public

    Forked from alexforencich/verilog-ethernet

    Verilog Ethernet components for FPGA implementation

    Verilog