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@opencomputeproject
Open Compute Project opencomputeproject

Austin, TX

@Essenceia
Julia Desmazes Essenceia
Designing ASICs for fun.

Austin

@cakehonolulu
Joel Bueno cakehonolulu
Systems Software (Firmware, Operating Systems & Security) Engineer | Low-level Ninja | He/Him | 24 | PFP by al_pansi

@openchip-sw Tarragona, Catalonia

@LCAI-TIHU
LCAI LCAI-TIHU

Inspur

@xianbaoqian
Tiezhen WANG xianbaoqian
@ashaltu
Abduselam ashaltu
@adam-maj
Adam Majmudar adam-maj
adammaj.com

thirdweb South Pole, Antarctica

@codecrafters-io
CodeCrafters codecrafters-io
Build your own Git, SQLite, & Redis.

United States of America

@Bogatell4
Bogatell4
@PacoReinaCampo
Francisco Javier Reina Campo PacoReinaCampo
I am an Electronic Engineer specialized in digital design and verification, with emphasis on Hardware Description Languages ((System)Verilog, VHDL).

QueenField Abu Dhabi

@bsc-loca
BSC LOCA bsc-loca
Barcelona Supercomputing Center (BSC) Laboratory for Open Computer Architecture (LOCA)

Spain

@Jbalkind
Jonathan Balkind Jbalkind

UC Santa Barbara

@ghdl
ghdl
@paunet
paunet
@pyuvm
pyuvm pyuvm
The UVM IEEE 1800.2 Standard implemented in Python
@verilator
Verilator verilator
Verilator Open-Source SystemVerilog simulator and lint system
@pulp-platform
pulp-platform
@riscv-admin
RISC-V Administrative Materials riscv-admin
The Open-Standard Instruction Set Architecture

Zurich, CH

@semidynamics-dev
Semidynamics semidynamics-dev
European provider of the finest RISC-V Cores and Vector Units

Semidynamics Technology Services Barcelona

@semidynamics
Semidynamics semidynamics
A European supplier of RISC-V IP cores, specializing in high performance vector cores targeted at AI applications.
@gem5
gem5 gem5
@riscv
RISC-V riscv
The Open-Standard Instruction Set Architecture

Zurich, CH

@stnolting
stnolting
Roads? Where we're going we don't need roads. - "Doc" Emmett L. Brown
@niekiran
Kiran Nayak niekiran
Firmware Engineering

FastBit Embedded Brain Academy

@aneto0
André Neto aneto0
@MartianGirl
MartianGirl