List of awesome open source hardware tools, generators, and reusable designs

Library of open source PDKs

RISC-V XV6/Linux SoC, marchID: 0x2b

mdBook preprocessor to add hover hints (tooltips) to your book

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure

A minimal GPU design in Verilog to learn how GPUs work from the ground up

HW Design Collateral for Caliptra RoT IP

OpenTitan: Open source silicon root of trust

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

Implementation of the PRINCE lightweight block cipher in VHDL.

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Master programming by recreating your favorite technologies from scratch.

Generator Bootcamp Material: Learn Chisel the Right Way

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Open-source high-performance RISC-V processor

Implementation of RouteNet, an effective way for Network Modeling and Optimization in SDN

CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port i…

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

Developed a Controllable SMPS with Shakti Parashu RISC-V FPGA in hardware (Verilog), wrote the software for it (in C), to control a DC-DC converter. Implemented UART(using interrupt architecture), …

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

Waveform Viewer Extension for VScode

Ariane SDK containing RISC-V tools and Buildroot

Test suite designed to check compliance with the SystemVerilog standard.

SonicBOOM: The Berkeley Out-of-Order Machine

SCR1 is a high-quality open-source RISC-V MCU core in Verilog