Wafer Fab Equipment Model
Bottoms-up from wafer capacity to tool demand: layer-by-layer lithography flows from the first EUV use to 1.4nm-class and high-NA, five equipment segments sized through 2028 with monthly updates, and a tool-level lithography database.
- Segments
- 5 tracked
- Vendors
- 20+ covered
- Forecasts
- Through 2028
- Cadence
- Monthly
A bottoms-up model of tool demand.
The SemiAnalysis Wafer Fab Equipment Model forecasts equipment sales the way fabs actually create demand: wafer capacity and process node requirements drive tool counts, layer by layer. Advanced logic flows are modeled in full, from the first EUV insertion through 1.4nm-class processes and high-NA EUV, across finFET, gate-all-around, and backside power delivery.
The result is a bottoms-up view of lithography, deposition, etch, wafer track, and metrology and inspection: segment sales through 2028 split across leading-edge logic, specialty, DRAM, NAND, and China, with a tool-level lithography database underneath.
Who uses it, and what it decides.
The buyers of this model, and the calls they make with it.
- Public & private market investors
- Positioning across ASML, Applied Materials, Lam Research, KLA, Tokyo Electron, and peers with demand derived from capacity plans and layer flows, not extrapolated from last quarter.
- Equipment & materials strategy teams
- Segment sizing and share shifts as nodes migrate: what gate-all-around, backside power, and high-NA EUV do to tool intensity in each segment.
- Chipmakers & fab planners
- Capex benchmarks by chipmaker and process, litho tool productivity comparisons, and the equipment implications of node roadmap choices.
- Supply chain & policy analysts
- China equipment demand tracked as its own end market, alongside leading-edge logic, specialty, DRAM, and NAND, through 2028.
From wafer starts to tool orders.
Capacity drives flows, flows drive tools, and every segment is sized from the bottom up.
The demand, derived
Wafer capacity and capital spending set the ceiling on every tool order:
Capacity by node
Leading-edge logic capacity through 2028, plus 10nm-class DRAM, node by node
Capex by chipmaker
Annual equipment capital expenditure by advanced logic chipmaker and process
Node timing
Ramp schedules by chipmaker and process node, so demand lands in the right year
Lithography, tool by tool
The deepest layer of the model is the scanner fleet itself:
Tool database
EUV, ArFi, and KrF tools with throughput, uptime, rework rate, release date, and ASP, including upcoming next-generation tools
Layer-by-layer flows
Lithography requirements per layer for advanced logic nodes, from first EUV use through 1.4nm-class
EUV futures
High-NA adoption, pattern shaping, and directed self-assembly, with their impact on EUV demand
Every segment, sized
Aggregate wafer fab equipment sales through 2028, split the way the market actually buys:
Five segments
Lithography, deposition, etch, wafer track, and metrology and inspection
Five end markets
Leading-edge logic, specialty, DRAM, NAND and non-volatile, and China
Vendor coverage
Applied Materials, ASML, Lam Research, KLA, Screen, ASMI, Kokusai Electric, Tokyo Electron, and more
The architecture shifts, priced in
FinFET to gate-all-around to backside power delivery: each architecture change rewrites tool intensity per wafer, and the model carries those flows explicitly so segment demand moves when the roadmap does, not after the vendors report it.
How wafer starts become tool orders.
The model is a chain of derivations: capacity plans set the wafer starts, layer flows turn starts into exposures and process steps, the scanner fleet sizes itself to carry them, and demand fans out across every equipment segment.
Stage 01 · Wafer capacity
Capacity sets the ceiling
Wafer starts by chipmaker and node, with ramp timing, decide how much equipment the industry can possibly need and when the orders land.
In the model: leading-edge logic capacity through 2028, plus 10nm-class DRAM, with capex by chipmaker and process
Stage 02 · Layer flows
Nodes decide the work per wafer
Layer-by-layer flows translate each node into exposures and process steps. FinFET, gate-all-around, and backside power each rewrite the count.
In the model: lithography requirements per layer from the first EUV use through 1.4nm-class, with pattern shaping and directed self-assembly scenarios
Stage 03 · Scanner fleet
Exposures become machines
Tool productivity turns exposure demand into scanner counts: throughput, uptime, and rework decide how many machines the flows require.
In the model: a tool-level database of EUV, ArFi, and KrF machines, and lithography sales by model, units, and revenue through 2028
Stage 04 · Five segments
Demand fans out across the fab
Every lithography pass drags track, etch, deposition, and metrology work with it, so the whole equipment market moves together.
In the model: aggregate wafer fab equipment sales through 2028 across five segments and five end markets, China broken out
Diagram of the model's derivation chain: wafer capacity feeds layer flows, layer flows size the scanner fleet, and demand fans out to five equipment segments. Selecting a stage shows its description.
The diagram is the shape of the model, not its output. Each stage carries the numbers in the workbook: capacity, layer flows, tool productivity, and segment sales through 2028.
How the model is built.
Capacity first, flows second, and the market total reconciled last.
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Start from capacity
Wafer capacity by node and chipmaker, with ramp timing and capex, sets how many tools each fab needs and when the orders land.
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Model the flows
Layer-by-layer process flows per node and architecture translate capacity into tool demand: litho passes drive track, etch, and deposition intensity, with tool productivity from the lithography database.
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Reconcile the market
Segment sales are checked against vendor results and chipmaker capex every quarter, and technology shifts like pattern shaping and directed self-assembly are priced into future EUV demand.
Research that ships with the model.
Model subscribers receive the update notes, webinars, and analysis published against each release. A sample of recent coverage:
Common questions.
Anything not covered here, ask the team directly through the form below.
What does the Wafer Fab Equipment Model include?
Wafer capacity forecasts for leading-edge logic and 10nm-class DRAM through 2028, lithography sales forecasts by tool model, units, and revenue, layer-by-layer lithography requirements from first EUV use through 1.4nm-class, aggregate wafer fab equipment sales across lithography, deposition, etch, wafer track, and metrology and inspection, capex by chipmaker and process, and a lithography tool database with throughput, uptime, rework, release dates, and ASPs.
Which vendors and end markets does it cover?
Applied Materials, ASML, Lam Research, KLA, Screen, ASMI, Kokusai Electric, Tokyo Electron, and more, with sales split across leading-edge logic, specialty including trailing-edge logic, analog, power, and RF, DRAM, NAND and non-volatile, and China.
How is the model built?
Bottoms-up: wafer capacity and process node requirements drive equipment sales. Layer-by-layer flows for advanced logic, across finFET, gate-all-around, and backside power delivery, translate capacity into tool demand, with lithography tool productivity from the database and technology shifts like high-NA EUV, pattern shaping, and directed self-assembly priced into future requirements.
How is the model delivered?
As an Excel model covering 2021 through 2028 on an annual basis, with one year of monthly updates, an initial consultation call on the model and methodologies, and ad-hoc follow-up calls for questions that come up in use.
Is it part of the SemiAnalysis newsletter subscription?
No. Industry models are separate institutional offerings and are not included with the annual newsletter membership.
Models that pair with this one.
The tools feed the fabs, the fabs ship the wafers, and the wafers become the chips. The other models cover each link.
Foundry Industry Model
The fabsThe customers of every tool this model counts: wafer shipments, capacity, and utilization across 19 foundries.
View model
Memory Model
The other fabsDRAM and NAND supply, demand, and pricing: the memory half of the equipment demand this model sizes.
View model
Accelerator & HBM Model
The chipsWhere the leading-edge capacity these tools build ultimately goes: accelerator shipments, SKU by SKU.
View modelGet the Wafer Fab Equipment Model.
Start with the sales team. They come back with scoping, licensing, and pricing for your mandate.
- Scoped to your use case
- Consultation and ad-hoc analyst calls included
- Custom research engagements available
