tag: DRAM

Hybrid Memory Combines NAND Flash And DRAM For Faster Data Transfer (U. of Seoul)
By Technical Paper Link - 29 Jul, 2026 - Comments: 0

Researchers from University of Seoul published a technical paper titled “NAD Memory: A Hybrid Memory Device Combined with NAND Flash Memory and DRAM.” The paper proposes "a hybrid memory architecture, termed NAD, which tightly integrates DRAM and NAND flash to enable direct and parallel data transfer. By eliminating intermediate components such as I/O buffers and data buses typically use... » read more

Data Center Chokepoints Tied To AI, Political Pressure, Supply Chain
By Brendan Heffernan - 20 Jul, 2026 - Comments: 0

Key Takeaways: AI-driven compute demands have led to several distinct supply chain bottlenecks for data centers. With data center energy demand surging faster than the grid can scale, small nuclear power has quickly moved to the center of the conversation. Hyperscalers have leaned into specialized facility design to meet their challenges, leading to an increasingly fragmented semicon... » read more

Open DRAM Model For PIM Analysis In 3D DRAM (Georgia Tech)
By Technical Paper Link - 12 Jul, 2026 - Comments: 0

Researchers from Georgia Institute of Technology published a technical paper titled “Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM.” Abstract Excerpt: “In this work, we present an “Open DRAM Model” that enables comprehensive circuit-level analysis of DRAM operations across multiple architectures, including conventional 6F2 BCAT, scaled 4F2 VCT, and monolit... » read more

Interference Risks In Processing-Using-DRAM (U. of Tokyo, ETH Zurich, CISPA, Riken)
By Technical Paper Link - 22 Jun, 2026 - Comments: 0

Researchers from The University of Tokyo, ETH Zurich, CISPA, and RIKEN published a technical paper titled “PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems.” Abstract excerpt: “We reveal PuDGhost, an interference phenomenon where a PuD operation in a given column produces erron... » read more

Will Your Chip’s Memory Work As Expected?
By Ed Sperling - 22 Jun, 2026 - Comments: 0

Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM
By Shyam Sharma - 11 Jun, 2026 - Comments: 0

DDR5 is the latest generation of DDR server memory capable of supporting data rates of up to 9,200 Mbps, which is a huge leap over the previous generation of DDR memories. It is used in a wide variety of applications, with the huge server and data center market being the key driver behind the adoption of DDR5-based memory systems. As systems move towards more CPU cores, bandwidth, and capacity,... » read more

SOCAMM2: Bringing LPDDR5X Benefits To AI Servers
By Piero Bianco - 14 May, 2026 - Comments: 0

The rapid scaling of artificial intelligence is reshaping nearly every dimension of data center design. While much of the focus has been on GPUs, accelerators and advanced packaging, another constraint is emerging as equally critical: power. As AI models grow larger and more complex, power consumption, not raw compute, is increasingly the limiting factor in system scalability. Modern AI work... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield
By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication
By Swapnil Kailash More - 16 Apr, 2026 - Comments: 0

By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

GPU Rowhammer Attacks Beyond Data Corruption (U. of Toronto)
By Technical Paper Link - 13 Apr, 2026 - Comments: 0

A new technical paper, "GPUBreach: Privilege Escalation Attacks via GPU Rowhammer," was published by researchers at University of Toronto. Summary "GPUBreach shows that GPU Rowhammer attacks can move beyond data corruption to real privilege escalation. By corrupting GPU page tables, an unprivileged CUDA kernel can gain arbitrary GPU memory read/write, and then chain that capability into CPU... » read more

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