verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
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Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
[UNRELEASED] FP div/sqrt unit for transprecision
RISC-V Debug Support for our PULP RISC-V Cores
Simple single-port AXI memory interface
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Generic Register Interface (contains various adapters)
Common SystemVerilog components
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
A minimal GPU design in Verilog to learn how GPUs work from the ground up
HW Design Collateral for Caliptra RoT IP